一种四采样低噪声CMOS光电探测器读出电路
A Four-Sampling Lower Noise Readout Circuit for CMOS Detector

DOI: 10.12677/OE.2019.92013, PP. 83-91

Keywords: 四采样，速率优化，低噪声，CMOS读出电路
Four Sampling, Rate Optimization, Low Noise, CMOS Readout Circuit

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Abstract:

为满足高采样速率可见光成像探测要求，本文设计了一种具有6 MHz采样频率的四采样长线列CMOS探测器。通过减小四采样后的第一级P跟随管宽长比降低总线寄生电容，和减小P跟随负载管偏置电压增加驱动电流，缩小信号延迟，使读出电路的采样频率由原来的2 MHz增加到6 MHz，有效地提高了长线列可见光CMOS探测器的读出频率。为实现真正相关双采样降低器件等效输入噪声，采用了CTIA积分放大器后接四采样跟随电路。通过测试，该CMOS探测器在积分时间为200 us、光敏面面积为20 um × 18 um的情况下其等效输入噪声电子数50e，与未采用四采样时相比较下降了50%左右。其线性度、输出摆幅、灵敏度等方面都能满足整机系统对CMOS探测器的指标要求。该CMOS探测器的研制为未来超高速高清晰成像探测奠定了重要的理论基础和实用基础。
In order to meet the requirements of high sampling rate of imaging detection, a four sampling long-line CMOS detector with 6 MHz sampling frequency is designed in this paper. By reducing the width to length ratio of the first stage P-type following transistor to decrease the bus parasitic capacitance and reducing the bias voltage of the P-type following load transistor to increase the driving current, thus the sampling frequency of the read-out circuit is increased from the original 2 MHz to the 6 MHz, which effectively improves the readout frequency of the long-line visible light CMOS detector. In order to achieve truely correlated double sampling and reduce the equivalent input noise of the device, the four sampling is used to connect CTIA integral amplifier. Through the test, the CMOS detector possesses an equivalent input noise electron less than 50e when the integral time is 200 us and the area of photosensitive is 20 um × 18 um, it can work steadily at the sampling rate of 6 MHz. The linearity, the output swing and the sensitivity of the detector can meet the requirements of the system. The development of the CMOS detector has laid an important theoretical foundation and practical value for the future ultra high speed and high definition imaging detection.

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