一种低资源数字抽取滤波器设计
Low Resource Consumption Design of Digital Decimation Filter

摘要 设计并实现一个应用于音频Sigma-Delta模数转换器的低资源数字抽取滤波器。该滤波器采用多级多采样率结构, 整体带内纹波小于0.06 dB, 带宽为21.6 kHz, 最低工作频率为10 MHz。通过滤波器硬件架构的设计, 有效地缩小了抽取滤波器的电路面积和功耗。芯片测试结果表明, 对 64 倍过采样率、4 阶Sigma-Delta调制的 1 bit 脉冲密度调制信号输出码流进行处理, 得到音频信号的信噪比达到87.2 dB, 在SMIC 0.13 μm 工艺下, 数字部分的面积约为0.146 mm2。与同类型抽取滤波器相比, 面积减小58%, 功耗减少60%以上。
Abstract A digital decimation filter applied to audio Sigma-Delta ADC is designed. The filter adopts the design of multi-stage and multi-rate down sampling structure, in-band ripple of decimation filter is less than 0.06 dB overall, bandwidth is 21.6 kHz, minimum working frequency is 10 MHz. Through the innovation of filter hardware architecture design, it effectively reduces the filter circuit area and power consumption. Chip test results show that the SNR is above 87.2 dB when processing PDM signals is at the down sampling rate of 64, 4 order Sigma-Delta modulation. Designed in SMIC’s 0.13 μm CMOS process, the decimation filter area is 0.146 mm2. Filter area is reduced by 58%, and power consumption is reduced by over 60% compared with the same type decimation filters.