|
|
- 2017
面向复杂电磁环境的容错电路系统设计技术
|
Abstract:
为解决复杂电磁环境中冗余容错电路系统容错形式单一、容错能力有限、冗余单元利用不充分和可靠性低等问题,提出了一种新颖的交互式？残？同故障容错(ICFT)技术。根据整个电路系统预期输出信号,利用硬件本身冗余无故障单元替换故障单元。结合硬件演化(EHW)和补偿平衡技术(RBT),当冗余无故障单元不足时,采用被动式ICFT技术对既有故障实现容错。当采用被动式ICFT技术失败时,采用主动式ICFT技术,通过注入故障并重新分配子电路功能实现容错。仿真结果表明:与常规冗余容错(CRFT)和硬件演化(EHW)相结合的技术CRFT？？EHW相比,采用ICFT技术能够容忍的工作电路最大故障单元累积量为41个,远大于采用CRFT？？EHW技术时的16个。
A novel design technology for fault tolerance circuit systems based on interactive？？collaborative fault tolerance (ICFT) technology is proposed to solve the problems that the redundant fault tolerance circuit systems have single fault tolerance form, their fault tolerance ability is limited, the use of redundant units is insufficient, and the reliability is low in complex electromagnetic environment. Fault units are replaced by redundant trouble？？free units according to the expected output signals of the whole circuit system. When there are not enough redundant trouble？？free units, the evolvable hardware (EHW) and the reparation balance technology (RBT) are combined, and then the passive？？ICFT technology is used to achieve fault tolerance for existing fault. The active？？ICFT is used only when the passive？？ICFT fails, and then sub？？circuit functions are redistributed. Simulation results show that the max faults units cumulative of working circuit of ICFT technology are forty？？one, which are far greater than sixteen of conventional redundant fault tolerance and EHW (CRFT？？EHW) technology
| [1] | ［8］WANG J, LEE C H. Virtual reconfigurable architecture for evolving combinational logic circuits ［J］. Journal of Central South University, 2014, 21(5): 1862？？1870. |
| [2] | ［9］ELNOKITY O E, MAHMOUD I I, REFAI M K, et al. Hardware implementation of virtual reconfigurable circuit for fault tolerant evolvable hardware system on FPGA ［J］. Lecture Notes in Engineering and Computer Science, 2014, 2(1): 7？？10. |
| [3] | ［10］ZHANG J B, CAI J Y, MENG Y F, et al. Fault self？？repair strategy based on evolvable hardware and reparation balance technology ［J］. Chinese Journal of Aeronautics, 2014, 27(5): 1211？？1222. |
| [4] | ［11］DHANASEKARAN D, BAGAN K B. Fault tolerant dynamic antenna array in smart antenna system using evolved virtual reconfigurable circuit ［C］∥Proceedings of 21st International Conference on VLSI Design. Piscataway, NJ, USA: IEEE, 2008: 77？？82. |
| [5] | ［12］NIAMAT M Y, HEJEEBU S S, ALAM M. A BIST approach for testing FPGAs using JBITS ［C］∥Proceedings of 13th Annual IEEE on Field？？Programmable Custom Computing Machines. Piscataway NJ, USA: IEEE, 2005: 267？？268. |
| [6] | ［13］GONG M, CAI Q, CHEN X, et al. Complex network clustering by multiobjective discrete particle swarm optimization based on decomposition ［J］. IEEE Transac？？tions on Evolutionary Computation, 2014, 18(1): 114？？130. |
| [7] | ［6］YAO X, HIGUCHI T. Promises and challenges of evolvable hardware ［J］. IEEE Transactions on Systems, Man, and Cybernetics: Part CApplications and Reviews, 1999, 29(1): 87？？97. |
| [8] | CHU Jie, MAN Menghua, CHANG Xiaolong, et al. Design of motor control circuit based on TMR？？EHW in complex electromagnetic environment ［J］. High Voltage Engineering, 2012, 38(9): 2314？？2321. |
| [9] | ［14］徐宇亮, 孙际哲, 陈西宏, 等. 采用多目标粒子群算法的模拟电路故障诊断研究 ［J］. 西安交通大学学报, 2012, 46(6): 92？？97. |
| [10] | ［15］刘新颖, 王曙鸿, 邱捷. 改进粒子群算法及其在超导电缆参数优化中的应用 ［J］. 西安交通大学学报, 2007, 41(2): 219？？223. |
| [11] | LIU Xinying, WANG Shuhong, QIU Jie. Improved particle swarm optimization with Its applications to parameter optimization of high temperature superconducting cables ［J］. Journal of Xi’an Jiaotong University, 2007, 41(2): 219？？223. |
| [12] | ［1］JOHN T. Self？？voting dual？？modular？？redundancy circuits for single？？event？？transient mitigation ［J］. IEEE Transactions on Nuclear Science, 2008, 55(6): 3435？？3439. |
| [13] | ［2］LEVITIN G, XING L D, DAI Y S. Optimal design of hybrid redundant systems with delayed failure？？driven standby mode transfer ［J］. IEEE Transactions on Systems, Man, and Cybernetics: Systems, 2015, 45(10): 1336？？1344. |
| [14] | ［3］LEVITIN G, XING L D, HANOCH B H. Effect of failure propagation on cold vs. hot standby tradeoff in heterogeneous 1？？out？？of？？N:G systems ［J］. IEEE Transactions on Reliability, 2015, 64(1): 410？？419. |
| [15] | ［4］ALMUKHAIZIM S, SINANOGLU O. Novel hazard？？free majority voter for n？？modular redundancy？？based fault tolerance in asynchronous circuits ［J］. IET Computers ＆ Digital Techniques, 2011, 5(4): 306？？315. |
| [16] | ［5］HADDOW P C, TYRRELL A M. Challenges of evolvable hardware: past, present and the path to a promising future ［J］. Genetic Programming and Evolvable Machines, 2011: 12(3): 183？？215. |
| [17] | ［7］褚杰, 满孟华, 常小龙, 等. 复杂电磁环境中高可靠性TMR？？EHW电机控制电路设计 ［J］. 高电压技术, 2012, 38(9): 2314？？2321. |
| [18] | XU Yuliang, SUN Jizhe, CHEN Xihong, et al. Analog circuit fault diagnosis with multi？？objective particle swarm optimization ［J］. Journal of Xi’an Jiaotong University, 2012, 46(6): 92？？97. |
| [19] | ［16］张峻宾, 蔡金燕, 李丹阳, 等. 三进制编码实现硬件演化方法研究 ［J］. 微电子学与计算机, 2013, 30(3): 1？？4. |
| [20] | ZHANG Junbin, CAI Jinyan, LI Danyang, et al. Research of ternary code implemented in hardware evolution ［J］. Microelectronics ＆ Computer, 2013, 30(3): 1？？4. |
