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- 2017
基于部分簇能量互补逻辑的MRF电路设计
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Abstract:
功耗是电路设计的关键性问题之一，低功耗下的稳定性问题逐渐成为电路设计的热点和挑战，基于马尔科夫随机场（MRF）的低功耗设计从能量的角度出发有效地解决了电路的容错问题，但是其单逻辑的单元结构面积和复杂度制约了该技术在大规模集成电路的应用。该文提出了一种基于部分簇能量的MRF电路设计方法（PMRF），并结合互补逻辑的特点来实现多逻辑结构，面积共享的同时一方面补偿由于部分簇能量带来的性能损失，一方面化简马氏随机场电路设计在较大规模电路设计中的面积和复杂度瓶颈问题。对比传统MRF电路设计，该文用PMRF方法设计了超前进位加法器结构，在低功耗仿真中具有20%的性能提升，并在65 nm TSMC版图实现后取得29%的面积节约和86%的功耗节约。
| [1] | REJIMON T, LING A, BHANJA S. Probabilistic error modeling for nano-domain logic circuits[J]. IEEE Trans VLSI, 2009, 17(1):55-65. |
| [2] | VAHID H, ALI P. A graph based approach for reliability analysis of nano-scale VLSI logic circuits[J]. Microelectronics Reliability, 2014, 54(3):1299-1306. |
| [3] | QIAN Li-bo, XIA Yin-shui, SHI Ge. Study of crosstalk effect on the propagation characteristics of coupled MLGNR interconnects[J]. IEEE Trans Nanotechnology, 2016, 15(5):810-819. |
| [4] | DING Wei-sheng, HSIEH H, HAN Cheng-yu. Test pattern modification for average IR-drop reduction[J]. IEEE Trans VLSI, 2016, 24(1):38-49. |
| [5] | SHIUE G H, YEH C L. Ground bounce noise induced by crosstalk noise for two parallel ground planes with a narrow open-stub line and adjacent signal traces in multilayer package structure[J]. IEEE Trans Components, 2014, 4(5):870-881. |
| [6] | HONG Jian, KIM S. Flexible ECC management for low-cost transient error protection of last-Level caches[J]. IEEE Trans VLSI, 2016, 24(6):2152-2164. |
| [7] | FARBEH H, KIM H. Floating-ECC:Dynamic repositioning of error correcting code bits for extending the lifetime of non-volatile caches[J]. IEEE Trans Computers, 2016, 16(99):1-10. |
| [8] | BAHAR R I, CHEN Jie. A probabilistic-based design for nanoscale computation[J] Nano, Quantum and Molecular Computing, 2004, 14(2):133-156. |
| [9] | NEPAL K, BAHAR R I, MUNDY J. Designing logic circuits for probabilistic computation in the presence of noise[C]//IEEE DAC. San Jose:ACM, 2005:485-490. |
| [10] | BAHAR R I, CHEN Jie. A probabilistic-based design for nanoscale computation[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2010, 5(14):21-36. |
| [11] | WEY I C, CHEN Y G. Design and implementation of cost-effective probabilistic-based noise-tolerant VLSI circuits[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2009, 56(11):2411-2420. |
| [12] | LI Yan, LI Xiao-qian, HU Jian-hao. Area-sharing cyclic structure MRF cirucits design in ultra-low supply voltage[C]//IEEE International Symposium on Circuits and Systems. Beijing:IEEE, 2015:2353-2356. |
| [13] | PARIHI K K. VLSI digital signal processing systems:Design and implementation[M]. Beijing:John Wiley & Sons, 2007:50-80. |
| [14] | BAHAR R I, CHEN Jie. A Probabilistic-based design for nanoscale computation[M]. Beijing:Academic Publishers, 2005:133-156. |
