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- 2016
容忍单粒子多节点翻转的三模互锁加固锁存器
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Abstract:
为了能够容忍单粒子多节点翻转,提出了一种新颖的三模互锁加固锁存器。该锁存器使用具有过滤功能的代码字状态保存单元(CWSP)构成三模互锁结构,并在锁存器末端使用CWSP单元实现对单粒子多节点翻转的容错。HSPICE仿真结果表明,相比于三模冗余(TMR)锁存器,该锁存器功耗延迟积(PDP)下降了58.93%;相比于容忍多节点翻转的DNCS-SEU锁存器,该锁存器的功耗延迟积下降了41.56%。同时该锁存器具有较低的工艺偏差敏感性。
[1] | PETERSEN E, KOGA R, SHOGA M A, et al. The single event revolution[J]. IEEE Transactions on Nuclear Science, 2013, 60(3):1824-1835. |
[2] | ZHU X W, DENG X W, BAUMANN R, et al. A quantitative assessment of charge collection efficiency of N+ and P+ diffusion areas in terrestrial neutron environment[J]. IEEE Transactions on Nuclear Science, 2007, 54(6):2156-2161. |
[3] | BLACK J D, BALL D R, ROBINSON W H, et al. Characterizing SRAM single event upset in terms of single and double node charge collection[J]. IEEE Transactions on Nuclear Science, 2008, 55(6):2943-2947. |
[4] | CALIN T, NICOLAIDIS M, VELAZCO R. Upset hardened memory design for submicron CMOS technology[J]. IEEE Transactions on Nuclear Science, 1996, 43(6):2874-2878. |
[5] | FAZELI M, PATOOGHY A, MIREMADI S G, et al. Feedback redundancy:a power efficient SEU-tolerant latch design for deep sub-micron technologies[C]//37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks. Edinburgh, UK:IEEE, 2007:276-285. |
[6] | NICOLAIDIS M. Time redundancy based soft-error tolerance to rescue nanometer technologies[C]//17<sup>th</sup> IEEE VLSI Test Symposium. Dana Point, CA, USA:IEEE, 1999:86-94. |
[7] | KATSAROU K, TSIATOUHAS Y. Double node charge sharing SEU tolerant latch design[C]//IEEE 20th Internation On-Line Testing Symposium (IOLTS). Platja d'Aro, Girona:IEEE, 2014:122-127. |
[8] | LIU B W, CHEN S M, LIANG B, et al. Temperature dependncy of charge sharing and MBU sensitivity in 130 nm CMOS technology[J]. IEEE Transactions on Nuclear Science, 2009, 56(4):2473-2479. |
[9] | RAJAEI R, TABANDEH M, FAZELI M. Single event multiple upset (SEMU) tolerant latch designs in presence of process and temperature variations[J]. Journal of Circuits, Systems and Computers, 2015, 24(01):1550007. |
[10] | NAN H Q, CHOI K. Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology[J]. Microelectronics Reliability, 2011(51):2086-2092. |
[11] | 刘必慰,郝跃,陈书明. SEU加固存储单元中的多节点翻转[J]. 半导体学报,2008, 29(2):244-250. LIU Bi-Wei, HAO Yao, CHEN Shu-min. Multiple node upset in SEU hardened storage cells[J]. Journal of Semiconductors, 2008, 29(2):244-250. |
[12] | RAJAEI R, TABANDEH M, RASHIDIAN B. Single event upset immune latch circuit design using C-element[C]//2011 IEEE 9th International Conference on ASIC.[S.l]:IEEE, 2011:252-255. |
[13] | ZHANG C Y, WANG Z S. A novel reliable SEU hardened latch to mitigate multi-node charge collecrion[C]//IET Internation Conference on Information Science and Control Engineering. Shenzhen, China:IET, 2012:1-4. |
[14] | ALESSIO M D, OTTAVI M, LOMBARDI F. Design of a nanometric CMOS memory cell for hardening to a single event with a multiple-node upset[J]. IEEE Transactions on Device and Materials Reliability, 2014, 14(1):127-132. |
[15] | CASEY M C, BHUVA B L, BLACK J D, et al. Single-event tolerant latch using cascode-voltage switch gates[J]. IEEE Transactions on Nuclear Science, 2006, 53(6):3386-3391. |
[16] | WEY I C, YANG Y S, WU B C, et al. A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design[J]. Microelectronics Journal, 2014(45):1-13. |
[17] | BAUMANN R C. Radiation-induced soft errors in advanced semiconductor technologies[J]. IEEE Transactions on Device and Materials Reliability, 2005, 5(3):305-316. |
[18] | BLACK J D, DODD P E, WARREN K M. Physics of multiple-node charge collection and impacts on single-event characterization and soft error rate prediction[J]. IEEE Transactions on Nuclear Science, 2013, 60(3):1836-1851. |
[19] | NAN H Q, CHOI K. High performance, low cost, and robust soft error tolerant latch designs for nanoscale CMOS technology[J]. IEEE Transactions on Circuits and Systems, 2012, 59(7):1445-1457. |