Low complexity SEU mitigation technique for SRAM-based FPGAs
Low complexity SEU mitigation technique for SRAM-based FPGAs

An internal single event upset (SEU) mitigation technique is proposed, which reads back the configuration frames from the static random access memory (SRAM)-based field programmable gate array (FPGA) through an internal port and compares them with those stored in the radiation-hardened memory to detect and correct SEUs. Triple modular redundancy (TMR), which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it, is used to enhance the reliability. Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation, size and weight. The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect space-borne facilities from SEUs.
An internal single event upset (SEU) mitigation technique is proposed, which reads back the configuration frames from the static random access memory (SRAM)-based field programmable gate array (FPGA) through an internal port and compares them with those stored in the radiation-hardened memory to detect and correct SEUs. Triple modular redundancy (TMR), which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it, is used to enhance the reliability. Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation, size and weight. The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect space-borne facilities from SEUs.