Small Segment Coalescing: A Hardware Acceleration Method of Receive Side for TCP/IP Processing
Small Segment Coalescing: A Hardware Acceleration Method of Receive Side for TCP/IP Processing

Dealing with a hardware acceleration method, small segment coalescing (SSC) was proposed to achieve the acceleration of TCP/IP processing in the receiving process. To reduce the number of data copy, CPU interruptions and TCP/IP processing, SSC combines small received TCP segments that belong to the same TCP/IP connection into a large TCP package in Network Interface Card (NIC). The whole process is implemented by hardware in NIC so that SSC remains transparent to upper drivers. Based on the intensive study on TCP/IP protocol and NIC mechanism, the coalescing policy is carefully designed to make sure that SSC can make a reasonable decision on whether or when to start or finish coalescing without delay. In addition, SSC is implemented and integrated into LCE5718, which is a totally self-designed dual-port Gigabit Ethernet controller. Finally, the simulation environment is constructed to verify the function of the design. A field programmable gate array (FPGA) prototype is set up, and experiments are conducted to show the performance of SSC in different configurations.
Dealing with a hardware acceleration method, small segment coalescing (SSC) was proposed to achieve the acceleration of TCP/IP processing in the receiving process. To reduce the number of data copy, CPU interruptions and TCP/IP processing, SSC combines small received TCP segments that belong to the same TCP/IP connection into a large TCP package in Network Interface Card (NIC). The whole process is implemented by hardware in NIC so that SSC remains transparent to upper drivers. Based on the intensive study on TCP/IP protocol and NIC mechanism, the coalescing policy is carefully designed to make sure that SSC can make a reasonable decision on whether or when to start or finish coalescing without delay. In addition, SSC is implemented and integrated into LCE5718, which is a totally self-designed dual-port Gigabit Ethernet controller. Finally, the simulation environment is constructed to verify the function of the design. A field programmable gate array (FPGA) prototype is set up, and experiments are conducted to show the performance of SSC in different configurations.