|
- 2015
基于随机映射的相变内存磨损均衡方法
|
Abstract:
相变内存(PCM)是一种使用相变材料存储数据的内存技术,具有非易失、存储密度高、低能耗和扩展性强等优点,但也存在写操作次数有限的缺陷。为了克服该问题,近期的研究主要集中在优化写操作和磨损均衡技术2个方面,但这些技术对于快速磨损PCM并使之失效的恶意攻击还存在一定的缺陷。该文提出一种PCM磨损均衡方法,将内存分成2个层级,不同的层级拥有各自独立的地址随机映射表,不同层级的内存单元根据该表将逻辑地址转换为物理地址。同时,地址随机映射表根据不同层级的写操作次数阈值进行动态更新。该方法不仅实现了PCM的磨损均衡,而且能够抵御恶意磨损程序的攻击。实验表明:相比已有的3种磨损均衡方法,该方法的磨损均衡效果提升高达87.5%;同时,对性能的影响不超过6%,增加的存储开销不超过内存总体大小的1‰。
Abstract:Phase change memory(PCM) uses a phase change material that is non-volatile, higher density, lower energy, and has better scalability than other methods. The main problem with PCM materials is the cell write limitation. Recent studies have focused on optimizing the write operations and wear-leveling, but cannot prevent malicious attacks to rapidly wear the PCM cells. This paper presents a PCM wear-leveling method which divides the whole PCM memory into two levels with separate random mapping tables to convert the logical cell addresses into physical addresses. The random mapping tables are updated dynamically according to the write count thresholds. This method not only implements PCM wear-leveling, but also resists malicious wearing-out attacks. Tests show that This method improves the wear-leveling by up to 87.5% over three existing wear-leveling methods with a system performance loss of less than 6% and additional storage overhead of less than 1‰ of the whole memory size.
[1] | Papandreou N, Pozidis H, Mittelholzer T, et al. Drift- tolerant multilevel phase-change memory[C]//Memory Workshop(IMW), 2011 3rd IEEE International. Monterey, CA, USA:IEEE press, 2011:1-4. |
[2] | Zhou P, Zhao B, Yang J, et al. A durable and energy efficient main memory using phase change memory technology[C]//Proceedings of the International Symposium on Computer Architecture(ISCA'09). New York, NY, USA:ACM, 2009:14-23. |
[3] | Qureshi M K, Karidis J, Franceschini M, et al. Enhancing lifetime and security of phase change memories via start-gap wear leveling[C]//Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture(MICRO 42). New York, NY, USA:ACM, 2009:14-23. |
[4] | Seong N H, Woo D H, Lee H H S. Security refresh:Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping[C]//Proceedings of the 37th Annual International Symposium on Computer architecture(ISCA'10). Saint-Malo, France:ACM, 2010:383-394. |
[5] | Binkert N, Beckmann B, Black G, et al. The gem5 simulator[J]. ACM SIGARCH computer architecture news, 2011, 39(2):1-7. |
[6] | Raoux S, Burr G W, Breitwisch M J, et al. Phase-change random access memory:A scalable technology[J]. IBM journal of research and development, 2008, 52(4/5):465-479. |
[7] | Shin D J, Park S K, Kim S M, et al. Adaptive page grouping for energy efficiency in hybrid PRAM-DRAM main memory[C]//Proceedings of the 2012 ACM Research in Applied Computation Symposium(RACS'12). New York, NY, USA:ACM, 2012:395-402. |
[8] | Yang B D, Lee J E, Kim J S, et al. A low power phase-change random access memory using a data- comparison write scheme[C]//Proceedings of IEEE International Symposium on Circuit and Systems(ISCAS 2007). New Orleans, LA, USA:IEEE press, 2007:3014-3017. |
[9] | Yang B D, Lee J E, Kim J S, et al. Flip-N-Write:A simple deterministic technique to improve PRAM write performance, energy and endurance[C]//Proceedings of the 42nd Annual International Symposium on Microarchitecture(MICRO-42). New York, NY, USA:IEEE press, 2009:347-357. |
[10] | Stan M R, Burleson W P. Bus-invert coding for low-power I/O[J]. IEEE transactions on very large scale integration(VLSI) systems, IEEE transactions on, 1995, 3(1):49-58. |
[11] | Bedeschi F, Fackenthal R, Resta C, et al. A multi-level-cell bipolar-selected phase-change memory[C]//Proceedings of the Solid-State Circuits Conference 2008(ISSCC 2008), Digest of Technical Papers, IEEE International. San Francisco, CA, USA:IEEE press, 2008:428-625. |
[12] | Knuth D E. Seminumerical algorithms. The Art of Computer Programming 2[M]. Boston, MA, USA:Addison-Wesley, 1969. |