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- 2017
时序电路有限状态机设计的安全性研究
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Abstract:
针对有限状态机优化设计过程中与功能无关的状态会带来的潜在安全问题，基于对其被侵入因素和攻击途径进行分析的基础上，提出了安全状态的定义，并实现了安全状态的设计方法。通过增加T触发器一个反馈信号，在不影响触发器功能条件下，对有限状态机进行状态保护。研究结果表明：添加状态自锁后的实验电路在功耗、时延和面积上要比原始实验电路提高了144.7%；优化T触发器后的实验电路在功耗上比原始实验电路降低了3。6%，在面积上降低了18.9%，在时延上提高了19.6%。
： In view of the potential security problems brought by the don't care state in the optimization of finite state machine (FSM), the definition of safe state and its design method are presented after analysis of the factors leading to intrusion into FSM and the attack paths. Without affecting the flip-flop function, state protection of FSM is realized by adding a feedback signal to the T-type flip-flop. Results show that the experimental circuit with state feedback signal is 144.7% higher than the original experimental circuit in the power consumption, delay and area; the experimental circuit optimized with T-type flip-flop is 3.6% lower than the original experimental circuit in power consumption, 18.9% lower in area, and 19.6% higher in delay
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