超低功耗无片外电容的低压差线性稳压器

为了减小无片外电容低压差线性稳压器（LDO）的功耗并提高稳定性，提出带有阻抗衰减缓冲器的LDO.该LDO主环路采用三级运放结构，具有动态偏置并联反馈结构和摆率增强电路的缓冲器作为中间级，驱动PMOS功率管.使用嵌套密勒补偿方式（NMC），将低频主极点放置在第一级输出，将缓冲器输出极点和LDO输出极点作为次极点构成极点-极点追踪，达到无片外电容LDO稳定性和瞬态响应的要求.芯片采用GSMC公司的130 nm CMOC工艺模型设计并经流片测试.测试结果表明：在1.6~4 V输入电压下，输出1.5 V电压，最大输出电流为1.5 mA时静态电流小于881 nA.测试结果验证了设计要求.
Abstract: A LDO with an impedance-attenuated buffer was proposed to reduce power consumption and enhance stability with no off-chip capacitor. The LDO main loop adopted three-stage amplifier structure. Dynamically-biased shut feedback structure and slew rate enhancement circuit were used as an intermediate buffer for driving the pass device. The dominant pole was put on the output of the first-stage and the non-dominant poles were put on the output of the buffer and the output of the pass device by using the method of nested Miller compensation (NMC), realizing pole-pole tracking frequency compensation. The properties of stability and transient responses meet the design requirements. The proposed LDO was designed and implemented by using GSMC 130 nm CMOS process. The measured results showed that the output voltage was stable at 1.5 V when its input voltage was set to be changed from 1.6 to 4 V. The quiescent current was measured to be less than 881 nA at 1.5 mA output current. The designed circuit was validated by the results of the chip test.