10 GHz低相噪扩频时钟发生器的设计与实现

基于55 nm CMOS工艺设计并制造了一款小数分频锁相环低相噪10 GHz扩频时钟发生器(SSCG).该SSCG采用带有开关电容阵列的压控振荡器实现宽频和低增益，利用3阶MASHΔΣ调制技术对电路噪声整形降低带内噪声，使用三角波调制改变分频系数使扩频时钟达到5 000×10-6.测试结果表明：时钟发生器的中心工作频率为10 GHz，扩频模式下峰值降落达到16.46 dB；在1 MHz频偏处的相位噪声为-106.93 dBc/Hz.芯片面积为0.7 mm×0.7 mm，采用1.2 V的电源供电，核心电路功耗为17.4 mW.
A 10 GHz low phase noise spread spectrum clock generator(SSCG) based on a fractional PLL in a 55 nm CMOS process was developed.The clock generator adopts a LC tank voltage-controlled oscillator (VCO) with switched capacitors array to obtain the wide-band frequency range and low gain, and the multi-stage noise shaping(MASH) modulating technology was utilized to shape and degrade in-band phase noise.The SSCG changes the division ratio with triangular modulation to achieve the goal of 5 000×10-6 spread spectrum clock.The measurements show that the clock generator operates at a 10 GHz, the peak reduction of electromagnetic interference (EMI) is 16.46 dB and the phase noise is -106.93 dBc/Hz@1 MHz in Spread Spectrum Clocking (SSC) Mode.The chip core area is less than 0.28 mm2 and the core power consumption is 17.4 mW at a supply of 1.2 V．