一种基于前馈网络的素数Sigma Delta〖WT〗调制器优化设计

Sigma Delta调制器是小数分频锁相环(Phase Locked Loop, PLL)中的关键模块，其噪声整形效果直接影响PLL的输出杂散、频率精度等性能.已有调制器均不能同时解决输出序列周期短、输出小数值无法覆盖0到1以及输出存在误差问题.针对这些问题，提出了一种新型的、基于前馈网络的素数调制器结构，使调制器的输出序列周期在任何输入值和初始值下都能达到M3，比传统调制器增大约M2/2倍，解决了已有调制器的输出序列周期短的问题，其中M为比2n0小的最大素数，n0为调制器中加法器的位数.提出的调制器还保证了输出小数值能够覆盖0~1、输出无误差.仿真结果表明，得益于输出序列周期更长，提出的调制器比已有的调制器更能有效去除输出量化噪声功率谱中的毛刺，噪声整形性能更接近理想调制器.
As the key module of fractional N PLL(Phase Locked Loop), the Sigma Delta modulator can significantly improve the performance of the fractional N PLL by the way of noise shaping. However, when it comes to the three most important specifications: the output sequence cycle, the range and the error, the now existing modulators cannot improve them at the same time. As a contrast, the proposed novel Sigma Delta modulator ameliorates the aforementioned three specifications simultaneously by adding a feed forward between two adjacent stages and adjusting the modulus of adders to prime number. Regardless of the input value and initial conditions, the presented modulator guarantees a sequence length of M3, which is almost M2/2 times of that in traditional modulator, where M is the largest prime number smaller than 2n0, and n0 is the bit width of adders. The simulation results show that, compared with the existing modulators, the proposed modulator can effectively remove the spur in the output spectrum and make it more close to the ideal Sigma Delta modulator.