基于新型结构的小面积全数字DDR接口模块

提出一种新型全数字鉴相器结构.该结构消除了亚稳态影,并通过采用特殊的延迟链结构,大大减少了模块的面积.将此结构应用于一款65 nm low leakage工艺下工作频率在100 ~400 MHz的全数字DDR接口模块,总面积4 298 μm2, DLL面积2 350 μm2.芯片的测试结果验证了设计的准确性,与传统的结构相比本模块面积较小，且由于其全数字电路的特点具有较好的可移植性.
This paper proposed a novel phase detector structure that prevent the effect of metastability,and using a inverted delay line structure to reduce its area.The structure was implemented in SMIC 65 nm low leakage tech node inside an all digital DDR PHY which can work in frequency from 100~400 MHz.The total area is 4 298 μm2 and the DLL has a area of 2 350 μm2,chip testing results shows the IP works as expected.And since its all digital,the design also has good transplantability.