Design of a 12-Gbit/s CMOS DNFFCGdifferential transimpedance amplifier

A 12-Gbit/s low-power, wide-bandwidth CMOS(complementary metal oxide semiconductor)dual negative feedback feed-forward common gate(DNFFCG)differential trans-impedance amplifier(TIA)is presented for the very-short-reach(VSR)optoelectronic integrated circuit(OEIC)receiver. The dominant pole of the input node is shifted up to a high frequency, and thus the bandwidth of the CMOS DNFFCG TIA is improved. Besides, two negative feedback loops are used to reduce the input impedance and further increase the bandwidth. The proposed TIA was fabricated using TSMC 0.18 μm CMOS technology. The whole circuit has a compact chip area, the core area of which is only 0.003 6 mm2. The power consumption is 14.6 mW excluding 2-stage differential buffers. The test results indicate that the 3 dB bandwidth of 9 GHz is achieved with a 1.8 V supply voltage and its trans-impedance gain is 49.2 dBΩ. The measured average equivalent input noise current density is 28.1 pA/Hz1/2. Under the same process conditions, the DNFFCG has better gain bandwidth product compared with those in the published papers.