A Highly Compatible Circular-Shifting Network for Partially Parallel QC-LDPC Decoder

DOI: 10.4236/ijcns.2017.105B003, PP. 24-34

Keywords: Partially Parallel Layered Decoding, Circular-Shifting Network, QC-LDPC Decoder, Arbitrary Expansion Factor

Full-Text   Cite this paper   Add to My Lib

Abstract:

The conventional methodology for designing QC-LDPC decoders is applied for fixed configurations used in wireless communication standards, and the supported largest expansion factor Z (the parallelism of the layered decoding) is a fixed number. In this paper, we study the circular-shifting network for decoding LDPC codes with arbitrary Z factor, especially for decoding large Z (Z P) codes, where P is the decoder parallelism. By buffering the P-length slices from the memory, and assembling the shifted slices in a fixed routine, the P-parallelism shift network can process Z-parallelism circular-shifting tasks. The implementation results show that the proposed network for arbitrary sized data shifting consumes only one times of additional resource cost compared to the traditional solution for only maximum P sized data shifting, and achieves significant saving on area and routing complexity.

References

[1]	Gallager, R. (1962) Low-Density Parity-Check Codes. IEEE Trans. Inf. Theory, IT-8, 21-28. https://doi.org/10.1109/TIT.1962.1057683
[2]	Fossorier, M.P.C. (2004) Quasicyclic Low-Density Parity-Check Codes from Circu-lant Permutation Matrices. IEEE Trans. Inf. Theory, 50, 1788-1793. https://doi.org/10.1109/TIT.2004.831841
[3]	Liu, C.H., Yen, S.W., Chen, C.L., Chang, H.C., Lee, C.Y., Hsu, Y.S. and Jou, S.J. (2008) An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications. EEE J. Solid-State Circuits, 41, 684-694. https://doi.org/10.1109/JSSC.2007.916610
[4]	Liu, C.H., et al. (2009) Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network. IEEE Transactions on Circuits and Systems II: Express Briefs, 56, 734-738. https://doi.org/10.1109/TCSII.2009.2027967
[5]	Rovini, M., Gentile, G. and Fanucci, L. (2007) Mulit-Size Circular Shifting Net-works for Decoders of Structured LDPC Codes. Electronics Letters, 43, 938- 940. https://doi.org/10.1049/el:20071157
[6]	Kuo, T.-C. and Willson, A.N. (2008) A Flexible Decoder IC for WiMAX QC-LDPC Codes. Custom Integrated Circuits Conference, CICC 2008, San Jose, CA, 527-530.
[7]	Rovini, M., Gentile, G., Rossi, F. and Fanucci, L. (2007) A Scalable Decoder Architecture for IEEE 802.11n LDPC Codes. Global Telecommunications Conference, GLOBECOM’07, Washington DC, 3270- 3274. https://doi.org/10.1109/glocom.2007.620
[8]	Wang, Z. and Cui, Z. (2007) Low-Complexity High-Speed Decoder Design for Qua-si-Cyclic LDPC Codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15, 104-114. https://doi.org/10.1109/TVLSI.2007.891098
[9]	Sun, Y. and Cavallaro, J.R. (2013) VLSI Architecture for Layered Decoding of QC-LDPC Codes With High Circulant Weight. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21, 1960-1964. https://doi.org/10.1109/TVLSI.2012.2220388
[10]	Brack, T., Alles, M., Kienle, F. and Wehn, N. (2006) A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding. 2006 IEEE 17th International Symposium on Personal, Indoor and Mobile Radio Commu-nications, Helsinki, 1-5. https://doi.org/10.1109/PIMRC.2006.254126
[11]	Chen, X.H., Lin, S. and Akella, V. (2010) QSN—A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders. IEEE Transactions on Circuits & Systems II Express Briefs, 57, 782-786. https://doi.org/10.1109/TCSII.2010.2067811

Full-Text