Nowadays, transistor technology is going toward the fully depleted architecture; the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.
References
[1]
An introduction to FD-SOI. STMicroelectronics NV. https://www.youtube.com/watch?v=uvV7jcpQ7UY
[2]
Hu, C. (2010) Modern Semiconductor Devices for Integrated Circuits. In: Modern Semiconductor Devices for Integrated Circuits, Pearson, New York, 259-290.
[3]
Hu, C. (2012) Thin-Body FinFET as Scalable Low Voltage Transistor. 2012 International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Hsinchu, 23-25 April 2012, 1-4.
[4]
Sharma, R., Baishya, S., Haldar, R. and Guha, K. (2014) Future Transistor for Hand-Held Devices. 2014 International Conference on Innovations in Engineering and Technology, 3, 749-752.
[5]
Asenov, A. (2013) FinFETs. IEEE Council on Electronic Design Automation, Presented at SISPAD. http://www.ieee-ceda.org https://www.youtube.com/watch?v=6LcTrp6SB3o
[6]
Federspiel, X., Angot, D., Rafik, M., et al. (2012) 28 nm Node Bulk vs. FDSOI Reliability Comparison. 2012 IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, 15-19 April 2012, 3B.1.1-3B.1.4.
[7]
Ma, F.Y., Je, M. and Hung, Y.L.Y. (2013) Singapore Sponsors Lectures on MOS Technology by SSCS DL Dr. Alvin Loke [Chapters]. IEEE Solid-State Circuits Magazine, 5, 96-98. https://doi.org/10.1109/MSSC.2013.2254649
[8]
Weber, O., Faynot, O., Andrieu, F., et al. (2008) High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and Its Physical Understanding. IEEE International Electron Devices Meeting, San Francisco, 15-17 December 2008, 1-4.
[9]
Thomas, O., Noel, J.-P., Fenouillet-Beranger, C., Jaud, M.-A., Dura, J. and Perreau, P. (2010) 32 nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From Device to Circuit. Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), Paris, 30 May-2 June 2010, 1703-1706. https://doi.org/10.1109/ISCAS.2010.5537517
[10]
Troutman, R.R. (1979) VLSI Limitation from Drain-Induced Barrier Lowering. IEEE Transactions on Electron Devices, 26, 461-469. https://doi.org/10.1109/T-ED.1979.19449
[11]
Chaudhry, A. and Kumar, M.J. (2004) Controlling Short-Channel Effects in Deep Submicron SOI MOSFETs for Improved Reliability: A Review. IEEE Transactions on Device and Materials Reliability, 4, 99-109. https://doi.org/10.1109/TDMR.2004.824359
[12]
Dghais, W. and Rodriguez, J. (2015) UTTB FDSOI Back-Gate Biasing for Low Power and High-Speed Chip Design. In: Mumtaz, S., Rodriguez, J., Katz, M., Wang, C. and Nascimento, A., Eds., Wireless Internet WICON 2014 Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, Vol. 146, Springer, Cham, 113-121. https://doi.org/10.1007/978-3-319-18802-7_16
[13]
Hu, C. (2011) FinFET and Other New Transistor Technologies. Presented at University of California.
[14]
Magarshack, P., Flatresse, P. and Cesana, G. (2013) UTBB FD-SOI: A Process/Design Symbiosis for Breakthrough Energy-Efficiency. Design, Automation & Test in Europe Conference & Exhibition, Grenoble, 18-22 March 2013, 952-957. https://doi.org/10.7873/date.2013.200
[15]
Noel, J.-P., Thomas, O., Jaud, M.-A., et al. (2011) Multi-VT UTBB FDSOI Device Architectures for Low-Power CMOS Circuit. IEEE Transactions on Electron Devices, 58, 2473-2482. https://doi.org/10.1109/TED.2011.2155658
[16]
Flatresse, P. (2013) UTBB-FDSOI Design & Migration Methodology. http://cmp.imag.fr/IMG/pdf/utbb-fdsoidesign_migration_methodology_.pdf
[17]
Schaeffer, J. (2015) Extending Moore’s Law with FD-SOI Technology. Global Foundaries Technical Webinar Series. https://www.chipestimate.com/ https://www.youtube.com/watch?v=7VmQlpXKtHE
[18]
Cesana, G. (2014) The FD-SOI Technology for Very High-Speed and Energy Efficient SoCs. http://www.soiconsortium.org/fully-depleted-soi/presentations/september-2014- fd-soi-forum/TP2521%20The%20FD-SOI%20technology%20for%20energy%20eff.pdf
[19]
What Is FD-SOI and Why Is It Useful? http://www.techdesignforums.com/practice/guides/fd-soi/
[20]
Rudenko, T., Kilchytska, V. and Collaert, N. (2008) Carrier Mobility in Undoped Triple-Gate FinFET Structures and Limitations of Its Description in Terms of Top and Sidewall Channel Mobilities. IEEE Transactions on Electron Devices, 55, 3532-3541. https://doi.org/10.1109/TED.2008.2006776
[21]
Bohr, M. and Mistry, K. (2011) Intel’s Revolutionary, 22 nm Transistor Technology. http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-details_ presentation.pdf
[22]
Doris, B., Khakifirooz, A., et al. (2014) Fully Depleted Devices FDSOI and FinFET. In: Brozek, T., Ed., Micro- and Nano-Electronics, CRC Press, Boca Raton, 71-93.
[23]
Agrawal, N., Kimura, Y., Arghavani, R. and Datta, S. (2013) Impact of Transistor Architecture (Bulk Planar, Tri-gate on Bulk, Ultrathin-Body Planar SOI) and Material (Silicon or III-V Semiconductor) on Variation for Logic and SRAM Applications. IEEE Transactions on Electron Devices, 60, 3298-3304. https://doi.org/10.1109/TED.2013.2277872
[24]
Dillinger, T. (2015) Tradeoffs in Bulk Planar FET, FD-SOI, and FinFET Design. IEEE Electronic Design Process Symposium.
[25]
Lee, K.W., An, T.Y., Joo, S.Y., Kwon, K.W. and Kim, S.Y. (2013) Modeling of Parasitic Fringing Capacitance in Multifin Tri-Gate FinFETs. IEEE Transactions on Electron Devices, 60, 1786-1789. https://doi.org/10.1109/TED.2013.2252467
[26]
Strojwas, A.J. (2013) Is the Bulk vs. SOI Battle over? 2013 International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Hsinchu, 22-24 April 2013, 1-2. https://doi.org/10.1109/VLSI-TSA.2013.6545649
[27]
Mohapatra, S.K., Pradhan, K.P., Singh, D. and Sahu, P.K. (2015) The Role of Geometry Parameters and Fin Aspect Ratio of Sub-20 nm SOI-FinFET: An Analysis towards Analog and RF Circuit Design. IEEE Transactions on Nanotechnology, 14, 546-554. https://doi.org/10.1109/TNANO.2015.2415555
