Study of Timing Characteristics of NOT Gate Transistor Level Circuit Implemented Using Nano-MOSFET by Analyzing Sub-Band Potential Energy Profile and Current-Voltage Characteristic of Quasi-Ballistic Transport
This paper presents the quasi-ballistic electron transport of a symmetric double-gate (DG) nano-MOSFET with 10 nm gate length and implementation of logical NOT transistor circuit using this nano-MOSFET. Theoretical calculation and simulation using NanoMOS have been done to obtain parameters such as ballistic efficiency, backscattering mean free path, backscattering coefficient, critical length, thermal velocity, capacitances, resistance and drain current. NanoMOS is an on-line device simulator. Theoretical and simulated drain current per micro of width is closely matched. Transistor loaded NOT gate is simulated using WinSpice. Theoretical and simulated value of rise time, fall time, propagation delay and maximum signal frequency of logical NOT transistor level circuit is closely matched. Quasi-ballistic transport has been investigated in this paper since modern MOSFET devices operate between the drift-diffusion and ballistic regimes. This paper aims to enable modern semiconductor device engineers to become familiar with both approaches.
References
[1]
Hosseini, R. and Teimuorzadeh, N. (2013) Simulation Study of Circuit Performance of GAA Silicon Nanowire Transistor and DG MOSFET. Physical Review & Research International, 3, 568-576.
[2]
Gowri Sankar, P.A. and Udhayakumar, K. (2014) MOSFET-Like CNFET Based Logic Gate Library for Low-Power Application: A Comparative Study. Journal of Semiconductors, 35, Article ID: 075001. https://doi.org/10.1088/1674-4926/35/7/075001
[3]
Wulf, U., Krah-lisch, M. and Richter, H. (2011) Scaling Properties of Ballistic Nano-Transistors. Nanoscale Research Letters, 6, 365. https://doi.org/10.1186/1556-276X-6-365
[4]
Baldo, M. (2011) Introduction to Nanoelectronics. MIT Open Course Ware Publication, May.
[5]
Navi, K., Rashtian, M., Khatir, A., Keshavarzian, P. and Hashemipour, O. (2010) High Speed Capacitor-Inverter Based Carbon Nanotube Full Adder. Nanoscale Research Letters, 5, 859-862. https://doi.org/10.1007/s11671-010-9575-4
[6]
Tan, M.L.P., Lentaris, G. and Amaratunga, G.A.J. (2012) Device and Circuit-Level Performance of Carbon Nanotube Field-Effect Transistor with Benchmarking against a Nano-MOSFET. Nanoscale Research Letters, 7, 467. https://doi.org/10.1186/1556-276X-7-467
[7]
Chin, H.C., Lim, C.S., Wong, W.S. and Tan, M.L.P. (2014) Enhanced Device and Circuit-Level Performance Benchmarking of Graphenenanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects. Journal of Nanomaterials, 2014, Article ID: 879813. https://doi.org/10.1155/2014/879813
[8]
Gupta, R., Tutuianu, B. and Pileggi, L.T. (1997) The Elmore Delay as a Bound for RC Trees with Generalized Input Signals. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 16, 95-104. https://doi.org/10.1109/43.559334
[9]
Li, Y.M. and Hwang, C.-H. (2008) High-Frequency Characteristic Fluctuations of Nano-MOSFET Circuit Induced by Random Dopants. IEEE Transactions on Microwave Theory and Techniques, 56, 2726-2733. https://doi.org/10.1109/TMTT.2008.2007077
[10]
Han, M.-H., Li, Y.M. and Hwang, C.-H. (2010) The Impact of High-Frequency Charactersitics Induced by Intrinsic Parameter Fluctuations in Nano-MOSFET Device and Circuit. Microelectronics Reliability, 50, 657-661. https://doi.org/10.1016/j.microrel.2010.01.048
[11]
Nasser, A.A.A., Aly, M.H., Abdel Rassoul, R.A. and Khourshed, A. (2011) Performance of Near-Ballistic Limit Carbon Nano-Transistor (CNT) Circuits. ICCTA, 175-182.
[12]
Ren, Z.B. (2011) Nanoscale MOSFETs: Physics, Simulation and Design. PhD Thesis, Purdue University.
[13]
Yee, O.C. and King, L.S. (2015) Simulation Study on the Electrical Performance of Equilibrium Thin-Body Double-Gate Nano-MOSFET. Jurnal Teknologi, 76, 87-95.
[14]
Yee, O.C. and King, L.S. (2016) Simulation Study of 2D Electron Density in Primed and Unprimed Subband Thin-Body Double-Gate Nano-MOSFET of Three Different Thicknesses and Two Temperature States. International Journal of Nanoelectronics and Materials, 9, 67-84.
[15]
Sinha, S.K. and Chaudhury, S. (2012) Simulation and Analysis of Quantum Capacitance in Single-Gate MOSFET, Double-Gate MOSFET and CNTFET Devices for Nanometer Regime. International Conference on Communications, Devices and Intelligent Systems, 28- 29 December 2012. https://doi.org/10.1109/CODIS.2012.6422160
