In this paper, a novel 10
Transistor Static Random Access Memory (SRAM) cell is proposed. Read and Write
bit lines are decoupled in the proposed cell. Feedback loop-cutting with single
bit line write scheme is employed in the 10 Transistor SRAM cell to reduce
active power consumption during the write operation. Read access time and write
access time are measured for proposed cell architecture based on Eldo SPICE
simulation using TSMC based 90 nm Complementary Metal Oxide Semiconductor
(CMOS) technology at various process corners. Leakage current measurements made
on hold mode of operation show that proposed cell architecture is having 12.31
nano amperes as compared to 40.63 nano amperes of the standard 6 Transistor
cell. 10 Transistor cell also has better performance in terms of leakage power
as compared to 6 Transistor cell.
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