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电子学报  2012 

防御零值功耗攻击的AESSubByte模块设计及其VLSI实现

DOI: 10.3969/j.issn.0372-2112.2012.11.007, PP. 2183-2187

Keywords: SubByte模块,零值功耗攻击,差分功耗攻击,加法性屏蔽,高级加密标准

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Abstract:

密码器件在执行高级加密标准(AdvancedEncryptionStandard,AES)时常以能量消耗方式泄漏密钥信息,为有效降低其与实际处理数据之间的相关性,该文提出一种具有防御零值功耗攻击性能的AESSubByte模块设计及其VLSI实现方案.首先,在分析GF(256)域求逆算法的基础上,采用关键模块复用的方法,提出一种更为有效的加法性屏蔽求逆算法;然后依此进一步得到一种新型的SubByte模块结构,实现在不影响对所有中间数据进行加法性屏蔽编码的同时,减少电路的芯片开销、提高电路的工作速度.实验结果表明,所设计的电路具有正确的逻辑功能.与传统SubByte模块比较,该设计的最高工作频率和面积都有较大的优化.

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