全部 标题 作者
关键词 摘要

OALib Journal期刊
ISSN: 2333-9721
费用:99美元

查看量下载量

相关文章

更多...
电子学报  2003 

VLSI集成电路参数成品率及优化研究进展

, PP. 1971-1974

Keywords: VLSI设计方法学,参数成品率,最优化设计

Full-Text   Cite this paper   Add to My Lib

Abstract:

VLSI的参数成品率是与制造成本和电路特性紧密相关的一个重要因素,随着集成电路(IC)进入超深亚微米发展阶段,芯片工作速度不断增加,集成度和复杂度提高,而工艺容差减小的速度跟不上这种变化,因此参数成品率的研究越来越重要.本文系统地讨论了参数成品率的模型和设计技术研究进展,分析不同技术的特点和局限性.最后提出了超深亚微米(VDSM)阶段参数成品率设计和成品率增强面临的主要问题及发展方向.

References

[1]  荆明娥,郝跃.VLSI成品率重心游移算法的一个几何解释[J].半导体学报,2004,25.
[2]  荆明娥,郝跃.集成电路分档成品率的效益优化模型及求解[J].西安电子科技大学学报,2004,31(2):
[3]  J W Bandler, Chen S H.Circuit optimization:the state of the art[J].IEEE Trans Microwave Theory and Techniques, 1988, 36(2):424-443.
[4]  Keramat M, Kielbasa R.Worst case efficiency of Latin hypercube sampling Monte Carlo(LHSMC) yield estimator of electrical circuits[A].Circuits and Systems, IEEE International Symposium[C].Hong Kong,1997.3.1660-1663.
[5]  Stephen W Director, Gary D Hachtel.Computationally efficient yield estimation procedures based on simplicial approximatio[J].IEEE Trans on CAS, 1978,25(3):121-129.
[6]  Say Wei Foo, Yu Lin.Hybrid method of tolerance design[A].Electronics, Circuits and Systems, Proceedings of ICECS''99[C].Pafos,Cyprus, 1999.1.557-560.
[7]  M Conti, P Crippa, S Orcioni, C Turchetti.Parametric yield optimization of MOS IC''s affected by device mismatch[A].Analog Integrated Circuits and Signal Processing[C].Netherlands:Kluwer Academic Publishers,2001.29(3).181-199.
[8]  Shen Y, Chen R M M.Application of genetic algorithm for response surface modeling in optimal statistical design[A].Circuits and Systems, IEEE International Symposium[C].USA, 1995.28(3).2152-2155.
[9]  Keramat M, Kielbasa R.OPTOMEGA:an environment for analog circuit optimization[A].Circuits and Systems.IEEE International Symposium[C].USA, 1998.6.122-125.
[10]  Hershenson M delM, Boyd S P Lee T H.Optimal design of a CMOS opamp via geometric programming[J].Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on,2001,20(1):1-21.
[11]  Conti M, Orcioni S, Turchetti C.Parametric yield optimization of MOS VLSI circuits based on simulated annealing and its parallel implementation[J].Circuits, Devices and Systems, IEE Proceedings, 1994, 141(5):387-398.
[12]  荆明娥,王宇平.基于产品最优分档的集成电路整体效益优化模型[J].西安电子科技大学学报,2002,29(2):300-304.
[13]  International Technology Roadmap for Semiconductors 2002 update[DB/OL].tech.Rep, Semiconductor industry association.http://public.itrs.net.
[14]  Jess J.Parametric yield estimation for deep sub-micron VLSI circuits,integrated circuits and systems design[A].Proceedings.15th Symposium on[C].Porto Allegre, Brazil, 2002.(15).387-388.
[15]  Martin haugh.Variance reduction(Ⅲ):Important Sampling, Monte Carlo simulation[DB/OL].IEOR E4703,2003.http://www.columbia.edu/~mh2078/MCSspring03/notes09.pdf.
[16]  Hany L Abdel-Malek, Abdel-karim S O Hassan.A boundary gradient search technique and its application in design centering[J].IEEE Trans on CAD,1999,18(11):1654-1661.
[17]  Zurada J M, Lozowski A, Malinowski A.Yield improvement for GaAs IC manufacturing using neural network inverse modeling[A].Neural Networks, International Conference on[C].USA, 1997.2.800-805.

Full-Text

Contact Us

service@oalib.com

QQ:3279437679

WhatsApp +8615387084133