S Lukas.EvolvableComponents:From Theory to Hardware Implementations[M].Berlin:Springer,2004.
[2]
A P Shanthi,R Parthasarathi.Practical and scalable evolution of digital circuits[J].Applied Soft Computing,2008,9(2):1-7.
[3]
何国良,李元香,史忠植.基于精英池演化算法的数字电路在片演化方法[J].计算机学报,2010,33(2):365-372. HE Guo-liang,LI Yuan-xiang,SHI Zhong-zhi.Elitist pool evolutionary algorithm for on-line evolution of digital circuits[J].Chinese Journal of Computers,2010,33(2):365-372.(in Chinese)
赵曙光,王宇平,杨万海,等.基于多目标自适应遗传算法的逻辑门级进化方法[J].计算机辅助设计与图形学学报,2004,16(4):402-406. Zhao Shuguang,Wang Yuping,Yang Wanhai,et al.Multi-objective adaptive genetic algorithm for gate-level evolution of logic circuits[J].Journal of Computer-Aided Design & Computer Graphics,2004,16(4):402-406.(in Chinese)
[6]
徐渊,杨波,朱明程,等.模拟褪火与遗传算法结合的数字FIR滤波器硬件进化算法[J].计算机辅助设计与图形学学报,2006,18(5):674-679. Xu Yuan,Yang bo,Zhu Mingcheng.A new genetic algorithm involving mechanism of simulated annealing for digital FIR evolving hardware[J].Journal of Computer-Aided Design & Computer Graphics,2006,18(5):647-679.(in Chinese)
[7]
汪鹏君,李辉,吴文晋,王伶俐,张小颖,戴静.量子遗传算法在多输出Reed-Muller逻辑电路最佳极性搜索中的应用[J].电子学报,2010,38(5):1058-1063. WANG Peng-jun,WU Wen-jin,WANG Ling-li,ZHANG Xiao-ying,DAI Jing.Application of quantum genetic algorithm in searching for best polarity of multi-output reed-muller logic circuits[J].Acta Electronica Sinica,2010,38(5):1058-1063.(in Chinese)
[8]
吴志波,张忠萍,陈菊平.基于FPGA的高重复率距离门控电路实现[J].电子学报,2010,38(4):919-0922. WU Zhi-bo,ZHANG Zhong-ping,CHEN Ju-ping.The implementation of range-gate control circuit with high repetition rate based on FPGA[J].Acta Electronica Sinica,2010,38(4):919-0922.(in Chinese)
[9]
P W Moore,G K Venayagamoorthy.Evolving digital circuits using hybrid particle swarm optimization and differential evolution[J].International Journal of Neural Systems,2006,16(3):163-177.
[10]
田海燕,曹鹏,王明飞,许鹏鹏,孟凡俊.宽带中频采样抗混迭滤波器的设计与实现[J].电子学报,2010,38(2A):60-64. TIAN Hai-yan,CAO Peng,WANG Ming-fei,XU Peng-peng,MENG Fan-jun.The design and implementation of the anti-aliasing filter for wideband IF signals sampling .Acta Electronica Sinica,2010,38(2A):60-64.(in Chinese)
[11]
X H Chen,YS Ong,M H Lim,K C Tan.A multi-facet survey on memetic Computation .IEEE Transactions on Evolutionary Computation,2011,15(5):591-608.
[12]
H shibuchi,Y Hitotsuyanagi,N Tsukamoto,Y Nojima.How to choose solutions for local search in multi-objective memetic algorithms .Proceedings of the 2010 International Workshop on Nature Inspired Computation and Applications .Hefei:USTC,2010.516-525.
[13]
Z G Bao,T Watanabe.A novel genetic algorithm with cell crossover for circuit design optimization .IEEE International Symposium on Circuits and Systems .Taipei,Taiwan:IEEE Press,2009.2982-2985.
[14]
S M Cheang,K H Lee,KS Leung.Applying genetic parallel programming to synthesize combinational logic circuits[J].IEEE transactions on evolutionary computation,2007,11(4):503-520.
[15]
梁厚军.电路进化设计算法研究 .合肥:中国科学技术大学,2009. Liang Hou-jun.Research on Evolutionary Design Algorithms for Circuits .Hefei,Anhui:University of Science and Technology of China,2009.(in Chinese)
[16]
林勇,罗文坚,王煦法.硬件电路的选择性进化冗余[J].中国科学技术大学学报,2006,36(5):523-529. LIN Yong,LUO Wen-jian,WANG Xu-fa.Selective redundancy of evolved circuits[J].Journal of University of Science and Technology of China,2006,36(5):523-529.(in Chinese)
[17]
姚睿,于盛林,王友仁,等.采用主流FPGA的数字电路在线生长进化设计方法[J].南京航空航天大学学报,2007,26(5):582-587. YAO Rui,YU Sheng-lin,WANG You-ren,et al.Online growing evolution and evaluation approach based on mainstream FPGA[J].Journal of Nanjing University of Aeronautics and Astronautics,2007,26(5):582-587.(in Chinese)
[18]
C Reis,J A Tenreiro Machado,J Boaventura Cunha.Evolutionary design of combinational logic circuits[J].Journal of Advanced Computational Intelligence and Intelligent Informatics,2004,8(5):507-513.
[19]
H G Beyer.The Theory of Evolution Strategies[M].Berlin,Heidelberg:Springer,2001.
[20]
J F Miller,P Thomson.Cartesian Genetic Programming[M].Edinburgh,UK:Springer Berlin,2000.
