全部 标题 作者
关键词 摘要

OALib Journal期刊
ISSN: 2333-9721
费用:99美元

查看量下载量

相关文章

更多...
电子学报  2013 

考虑时间因素的不同基本门故障概率计算

DOI: 10.3969/j.issn.0372-2112.2013.04.007, PP. 666-673

Keywords: 时间因素,输入负载,输入导线,CMOS器件,不同基本门的故障概率

Full-Text   Cite this paper   Add to My Lib

Abstract:

在门级电路的可靠性概率评估方法中,基本门的故障概率p一般人为设定或以常数形式出现.考虑到不同基本门的故障概率具有随时间变化的特性并结合其输入导线,本文构建了考虑输入负载的随时间变化的不同基本门的故障概率模型.理论分析与实验结果表明,基于弱链接模型的双峰对数正态分布更适合用来表示输入导线故障概率的时间分布.用本文方法、美国军用标准MIK-HDBK-217及MonteCarlo方法计算了ISCAS85基准电路的可靠度并进行了比较,还通过了行业标准的检验,结果验证了本文所构建模型的合理性.

References

[1]  J Xiao,J-H Jiang,X-G Zhu.A method of gate-level circuit reliability estimatio n based on iterative PTM model[A].Proceeding of IEEE 17th Pacific Rim Interna tional Symposium on Dependable Computing[C].Los Alamitos:IEEE Computer Society ,2011.276-277.
[2]  Han J,Hao C,Erin B.Reliability evaluation of logic circuits using probabilistic gate models[J].Microelectron Reliability,2011,51(2):468-476.
[3]  肖杰,江建慧.结合版图结构信息的基本门电路故障概率估计[J].电子学报,2012,40(2):23 5-240. Xiao Jie,Jiang Jian-hui.The estimation of fault probability of elementary gates based on the layout structure information[J].Acta Electronica Sinica,2012,40( 2):235-240.(in Chinese)
[4]  J-X Fang,S S Sapatnekar.Scalable methods for the analysis and optimization of g ate oxide breakdown[A].Proceeding of IEEE 11th International Symposium on Qual ity Electronic Design[C].Los Alamitos:IEEE Computer Society,2010.638-645.
[5]  MIL-HDBK-344A.Military handbook:Environmental stress screening of electronic e quipment[S].
[6]  Li B Z,Christiansen C,Gill J,et al.Threshold electromigration failure time and i ts statistics for Cu interconnects[J].Journal of Applied Physics,2006,100(1145 16):1-10.
[7]  Wu E Y,Sune J.Power law voltage acceleration:a key element for ultra-thin gate oxide reliability[J].Microelectronic Reliability,2005,45(12):1809-1834.
[8]  Wu E Y,Nowak W J,Vayshenker A,et al.CMOS scaling beyond the 100-nm node with si licon-dioxide-based gate dielectrics[J].IBM Journal of Research and Developm ent,2002,46(2/3):287-298.
[9]  Jong H P,Byung T A.Electromigration model for the prediction of lifetime based o n the failure unit statistics in aluminum metallization[J].Journal of Applied Physics,2003,93(2):883-892.
[10]  王真,江建慧.基于概率转移矩阵的串行电路可靠度计算方法[J].电子学报,2009,37(2):24 1-247. WANG Zhen,JIANG Jian-hui.A serial method of circuit reliability calculation bas ed on probabilistic transfer matrix [J].Acta Electronica Sinica,2009,37(2):241 -247.(in Chinese)
[11]  王真,江建慧.考虑版图级因素的PTM中故障感染率的计算[J].哈尔滨工业大学学报,2009,4 1(S):124-129. Wang Zhen,Jiang Jian-hui.The calculation of fault infection probability in PTM considering factors of layout[J].Journal of Harbin Institute of Technology,200 9,41(S):124-129.(in Chinese)
[12]  Liew B K,Fang P,Hu C M.Circuit reliability simulator for interconnect,via,and co ntact electromigration[J].IEEE Transactions on Electronic Devices,1992,39(11) :2472-2479.
[13]  Fischer A H,Abel A,Lepper M,et al.Modeling bimodal electromigration failure dist ributions[J].Microelectronics Reliability,2001,41(3):445-453.
[14]  辛维平,庄奕琪,李小明.片上栅氧化经时击穿失效监测电路与方法[J].电子学报,2012,40(11):2188-2193. Xin Wei-ping,Zhuang Yi-qi,Li Xiao-ming.An on-chip circuit for monitoring fai lure due to TDDB[J].Acta Electronica Sinica,2012,40(11):2188-2193.(in Chinese)

Full-Text

Contact Us

service@oalib.com

QQ:3279437679

WhatsApp +8615387084133