欧阳一鸣,张一栋,梁华国.三维片上网络故障及拥塞感知的容错路由器设计[J].电子学报,2013,41(05):912-917. Ouyang Yi-ming,Zhang yi-dong,Lian Hua-guo.A fault-tolerant design of congestion-aware router in three-dimensional network-on-chip[J].Acta Electronica Sinica,2013,41(05):912-917.(in Chinese)
[3]
Zhang,Zhen,Alain Greiner,Sami Taktak.A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip[A].Proceedings of Design Automation Conference[C].Anaheim:ACM/IEEE,2008.441-446.
[4]
Feng Chaochao,Minxuan Zhang.A low-overhead fault-aware deflection routing algorithm for 3D network-on-chip[A].Proceedings of 2011 IEEE Annual Symposium on Computer Society[C].Chennai:IEEE,2011.19-24.
[5]
Constantinides,Kypros,Stephen Plaza,Jason Blome.Bulletproof:A defect-tolerant CMP switch architecture[A].Proceedings of the Twelfth International Symposium on High-Performance Computer Architecture[C].Austin:IEEE,2006.5-16.
[6]
Latif,Khalid,A-M Rahmani,Ethiopia Nigussie,Hannu Tenhunen,Tiberiu Seceleanu.A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip[A].Proceedings of 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems [C].Vancouver:IEEE,2011.454-462.
[7]
Dally,William James Brian Patrick Towles,Principles and Practices of IntercoNnection networks[M].Access Online via Elsevier,2004.12-25.
[8]
刘家俊,顾华玺,王长山.mesh优先级容错路由[J].计算机工程与应用,2009,45(4):105-107. Liu Jia-jun,Gun-Huaxi,Wang Chang-shan.Priority fault-tolerant routing in mesh[J].Computer engineering and applications,2009,45(4):105-107.(in Chinese)
[9]
Nguyen,Son Truong and Shigeru Oyanagi.A low cost single-cycle router based on virtual output queuing for on-chip networks[A].Proceedings of 13th Euromicro Conference on Digital System Design:Architectures,Methods and Tools[C].Lille:IEEE,2010.60-67.
[10]
Tamir,Yuval and Gregory L Frazier,High-performance multi-queue buffers for VLSI communications switches[J].ACM,1988,16(02):343-354.
[11]
Mullins,Robert,Andrew West,and Simon Moore.The design and implementation of a low-latency on-chip network[A].Proceedings of the 2006 Asia and South Pacific Design Automation Conference[C].Piscataway:IEEE,2006.164-169.
[12]
Tran,Anh T,Bevan M Baas.RoShaQ:High-Performance On-Chip Router with Shared Queues[A].Proceedings of 2011 IEEE 29th International Conference on Computer Design[C].Amherst:IEEE,2011.232-238.
[13]
Park,Dongkook,Chrysostomos Nicopoulos.Exploring fault-tolerant network-on-chip architectures[A].Proceedings of International Conference on Dependable Systems and Networks[C].Philadelphia:IEEE,2006.93-104.
[14]
Glass,Christopher J and Lionel M Ni.The turn model for adaptive routing[A].Proceedings of ACM SIGARCH Computer Architecture News[C].New York:ACM,1992:278-287.
[15]
Zimmer,Heiko,Axel Jantsch.A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip[A].Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis[C].New York:ACM,2003.188-193.
[16]
Pullini,Antonio,Federico Angiolini.Fault tolerance overhead in network-on-chip flow control schemes[A].Proceedings of 18th Symposium on Integrated Circuits and Systems Design[C].Florianopolis:IEEE,2005.224-229.
[17]
Killian,Cédric,Camel Tanougast.A new efficient and reliable dynamically reconfigurable network-on-chip[J].Journal of Electrical and Computer Engineering,2012,2012(2012):1-16.
[18]
Khalid Latif,Ethiopia Nigussie,Martin Radetzki.Partial virtual channel sharing:A generic methodologyto enhance resource management and fault tolerancein networks-on-chip[J].Journal of Electronic Testing-theory and Applications,2013,29(03):1-22.
[19]
Liu,Cheng,Lei Zhang,Yinhe Han,Xiaowei Li.Vertical interconnects squeezing in symmetric 3D mesh network-on-chip[A].Proceedings of the 16th Asia and South Pacific Design Automation Conference[C].Piscataway:IEEE,2011.357-362.
[20]
Fick,David,Andrew DeOrio,Jin Hu,Valeria Bertacco,David Blaauw,Dennis Sylvester.Vicis:a reliable network for unreliable silicon[A].Proceedings of the 46th Annual Design Automation Conference[C].New York:ACM,2009.812-817.
[21]
欧阳一鸣,成丽丽,梁华国.一种基于变长数据块相关性统计的测试数据压缩和解压方法[J].电子学报,2008,36(12):298-302 Ouyang Yi-ming,Cheng Li-li,Lian Hua-guo.A new test data compression technique based on static relativity of variable length data block[J].Acta Electronica Sinica,2008,36(12):298-303.(in Chinese)
[22]
马立伟,孙义和.片上网络拓朴优化:在离散平面上布局与布线[J].电子学报,2007,35(05):p.906-911. Ma Li-wei,Sun Yi-he.Network-on-chip topology optimizations:floor-plan and routing on discrete plan[J].Acta Electronica Sinica,2007,35(05):906-911.(in Chinese)
