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电子学报  2014 

一个面向缺陷分析的电路成品率与可靠性的关系模型

DOI: 10.3969/j.issn.0372-2112.2014.04.020, PP. 747-755

Keywords: 门级电路的成品率与可靠性,缺陷的生长特性,广义门,版图结构信息,拓扑结构

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Abstract:

在电路设计的早期阶段,成品率与可靠性的关系模型对于预测和改善电路的成品率和可靠性具有极为重要的意义.结合广义门电路的版图结构与拓扑结构信息,分析了其缺陷密度及成品率和可靠性的损失机理,并构建了考虑缺陷生长特性的广义门电路成品率与可靠性损失概率之间的解析关系模型.基于该模型,又考虑到电路拓扑结构对故障的屏蔽效应,利用迭代的概率转移矩阵方法给出了门级电路成品率与可靠性之间的量化关系.理论分析与通过在ISCAS85基准电路上采用经验公式和惯用方法的证明策略,验证了本文所提方法的合理性和有效性.还分析了工艺参数、老化因素等对电路成品率与可靠性关系的影响.

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