Philip Garrou, Wafer level chip scale packaging (WL-CSP):an overview[J].IEEE Transactions on Advanced Packaging, 2000, 23(2):198-205.
[2]
尹立孟, 张新平.电子封装微互连中的电迁移[J].电子学报, 2008, 36(8):1610-1614. Yin Li-meng, Zhang Xin-ping.Electromigration in micro-interconnections of electronic packaging[J].Acta Electronica Sinica, 2008, 36(8):1610-1614.(in Chinese )
[3]
阮刚, 等.VLSI电路中互连线的延迟及串扰的数值模拟[J].电子学报, 2000, 28(5): 142-144. Ruan Gang, et al.Numerical simulation of time delay and cross-talk noise for the interconnect in VLSI circuits[J].Acta Electronica Sinica, 2000, 28(5):142-144.(in Chinese )
[4]
李志国, 卢振钧.ULSI中铜互连线通孔电热性能的数值模拟[J].电子学报, 2003, 31(7):1104-1106. Li Zhi-guo, et al.Numerical simulation of electric and thermal characteristic in ULSI copper-filled inteconnect via hole[J].Acta Electronica Sinica, 2003, 31(7):1104-1106.(in Chinese)
[5]
C C Yang, et al.Stress control during thermal annealing of copper interconnects[J].Applied Physics Letters, 2011, 98:051911-051913.
[6]
S-K Ryu, et al.Characterization of thermal stresses in through-silicon vias for three-dimensional interconnects by bending beam technique[J].Applied Physics Letters, 2012, 100:041901-041904.
[7]
P C Andricacos, et al.Damascene copper electroplating for chip interconnections.IBM Journal of Research and Development, 1998, 42(5):567-574.