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采用输入输出分解的分区分段演化机制

DOI: 10.3969/j.issn.1006-7043.201311105

Keywords: 演化硬件, 组合电路, 输入输出分解, 并行演化, 演化算法

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Abstract:

针对演化硬件的可扩展性问题,提出了基于输入输出分解的分区分段并行在线演化机制,用于演化组合逻辑电路.依据输入输出分解策略,将原电路分解为多个具有较少输入、输出的子电路,并对各子电路单独分配进化区域,实现各子电路的并行演化;某些子电路演化完毕,其对应进化区域即可用于其他任何未演化完毕子电路的并行演化;所有子电路均演化成功后,将其进行整合得到顶层电路.在Xilinx Virtex-5 FX构建的自演化系统上,以加法器电路、乘法器电路和部分MCNC基准电路为例进行了验证.结果表明:相对于经典演化方法,该方法可以大大减少演化时间,进化出多达21个输入的组合电路.

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