LIN B, IRIE M. Evolvable hardware[J]. CIT595 Research Project, 2008, 4(8): 162-164.
[2]
平建军, 王友仁, 高桂军,等. 数字演化硬件的函数级在线进化技术研究[J]. 高技术通讯, 2009, 19(1): 61-65.PING Jianjun, WANG Youren, GAO Guijun, et al. Research on the technology for on-line evolution of digital hardware at function level[J]. Chinese High Technology Letters, 2009,19(1):61-65.
[3]
吴江, 唐常杰, 李太勇,等. 基于多目标并行基因表达式编程的电路演化算法[J]. 武汉大学学报: 工学版, 2012, 45(4): 532-538.WU Jiang, TANG Changjie, LI Taiyong, et al. Evolutionary algorithm of circuits based on multi-objective parallel gene expression programming[J]. Engineering Journal of Wuhan University, 2012, 45(4): 532-538.
[4]
何国良, 李元香, 史忠植. 基于精英池演化算法的数字电路在片演化方法[J]. 计算机学报, 2010, 33(2): 365-372.HE Guoliang, LI Yuanxiang, SHI Zhongzhi. Elitist pool evolutionary algorithm for on-line evolution of digital circuits[J]. Chinese Journal of Computers, 2010, 33(2): 365-372.
[5]
BIDLO M. Evolutionary design of generic combinational multipliers using development[C] //7th International Conference Evolvable Systems: from Biology to Hardware. Wuhan, China, 2007: 77-88.
[6]
STOMEO E, KALGANOVA T, LAMBERT C. Generalized disjunction decomposition for evolvable hardware[J]. IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics, 2006, 36(5): 1024-1043.
[7]
王婷. 基于演化硬件的可重构技术研究[D]. 郑州:解放军信息工程大学, 2012:24-32.WANG Ting. Research on reconfigurable technology based on evolvable hardware[D]. Zhengzhou: The PLA Information Engineering University, 2012: 24-32.
[8]
ZHAO S, JIAO L. Multi-objective evolutionary design and knowledge discovery of logic circuits based on an adaptive genetic algorithm[J]. Genetic Programming and Evolvable Machines, 2006, 7(3): 195-210.
[9]
莫宏伟, 徐立芳. 基于Memetic 算法的电路演化设计研究[J]. 电子学报, 2013,41(5):1036-1040.MO Hongwei, XU Lifang. Research on evolvable hardware design based on memetic algorithm[J]. Acta Electronica Sinica, 2013, 41(5): 1036-1040.
[10]
STOMEO E, KALGANOVA T. Improving EHW performance introducinga new decomposition strategy[C] // 2004 IEEE Conference on Cybernetics and Intelligent Systems. Singapore, 2004: 439-444.
[11]
王进, 李丽芳, 任小龙. 多核虚拟可重构结构加速逻辑电路演化设计的研究[J]. 高技术通讯, 2012, 22(4): 340-347.WANG Jin, LI Lifang, REN Xiaolong. Using MuViRaC to accelerate evolutionary design of combinational logic circuits[J]. Chinese High Technology Letters, 2012, 22(4): 340-347.
[12]
ZHANG X, LUO W. Evolutionary repair for evolutionary design of combinational logic circuits[C] // 2012 IEEE Congress on Evolutionary Computation (CEC). Brisbane, Australia, 2012: 1-8.