全部 标题 作者
关键词 摘要

OALib Journal期刊
ISSN: 2333-9721
费用:99美元

查看量下载量

相关文章

更多...

片上网络的访存延迟均衡性

, PP. 1624-1630

Keywords: 通信技术,片上网络,访存延迟,众核架构,仲裁技术,均衡性

Full-Text   Cite this paper   Add to My Lib

Abstract:

对片上网络访存延迟均衡性展开了研究,提出基于总延迟预测的访存报文仲裁技术。首先,依据访存报文后续路径的拥塞信息预测访存报文未来等待延迟,并计算出总延迟。其次,基于预测的总延迟对竞争同一链路的访存报文进行仲裁。在Mesh片上网络路由器中,对该技术进行了设计和实现。实验结果表明:在不同的网络规模和报文注入率下,与经典Round-Robin仲裁机制相比,本文技术能够极大减少片上访存的最大延迟和延迟标准差,减少平均延迟,证明能够获得更佳的访存延迟均衡性。

References

[1]  Majo Z, Gross T R. Memory system performance in a NUMA multicore multi-processor[C]∥Proceedings of the 4th Annual International Conference on Systems and Storage, Haifa, Israel, 2011: 1-10.
[2]  Mutlu O, Moscibroda T. Stall-time fair memory access scheduling for chip multiprocessor[C]∥Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Chicago, US, 2007: 146-160.
[3]  Daneshtalab M, Ebrahimi M, Plosila J, et al. CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems[C]∥Proceedings of Design, Automation and Test in Europe Conference (DATE'13), Grenoble, France, 2013:1048-1051.
[4]  Kim D, Yoo S, Lee S. A network congestion-aware memory controller[C]∥Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, 2010:257-264.
[5]  Zhang G, Wang H, Chen X, et al. Fair memory access scheduling for quality of service guarantees via service curves[C]∥Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, Madrid, Spain, 2012: 174-181.
[6]  Jang W, Pan D. An SDRAM-aware router for networks-on-chip[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, 29(10): 1572-1585.
[7]  Pimpalkhute T, Pasricha S. Noc scheduling for improved application-aware and memory-aware transfers in multi-core systems[C]∥Proccedings of the 27th International Conference on VLSI Design and the 13th International Conference on Embedded Systems, Mubai ,India,2014:234-239.
[8]  刘胜, 陈书明, 尹亚明, 等. 片上网络延时差异对存储系统公平性的影响及对策[J]. 计算机学报,2011,34(8):1500-1508. Liu Sheng,Chen Shu-ming,Yin Ya-ming,et al.The effect of NoC latency difference on the fairness of memory systems and a strategy[J].Chinese Journal of Computers,2011,34(8):1500-1508.
[9]  Sharifi A, Kultursay E, Kandemir M, et al. Addressing end-to-end memory access latency in noc-based multicores[C]∥Proccedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'12), Vancouver, BC, Canada, 2012:294-304.
[10]  Dally W J. Virtual-channel flow control[J]. IEEE Transactions on Parallel and Distributed Systems, 1992, 3(2):194-205.
[11]  Kumar A, Peh L, Kundu P, et al. Express virtual channels: towards the ideal interconnection fabric[C]∥Proceedings of the 34th Annual International Symposium on Computer Architecture (ISCA'07), San, Diego, US, 2007:150-161.
[12]  Horowitz M, Dally W. How scaling will change processor architecture[C]∥International Solid-State Circuits Conference (ISSCC'04), San Francisco, US, Digest of Technical Papers, 2004:132-133.
[13]  Borkar S. Thousand core chips: a technology perspective[C]∥Proceedings of the 44th Design Automation Conference (DAC'07), San Diego, US, 2007:746-749.
[14]  Owens J D, Dally W J. Research challenges for on-chip interconnection networks[J]. IEEE Micro, 2007, 27(5):96-108.
[15]  Marinissen E, Prince B, Keltel-Schulz D, et al. Challenges in embedded memory design and test[C]∥Proceedings of Design, Automation and Test in Europe Conference (DATE'05), Munich, Germany, 2005:722-727.
[16]  Genius D. Measuring memory access latency for software objects in a NUMA system-on-chip architecture[C]∥Proceedings of the 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCo -SoC), Darmstadt, Germany, 2013: 1-8.

Full-Text

Contact Us

service@oalib.com

QQ:3279437679

WhatsApp +8615387084133