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高电源噪声抑制比带隙基准源设计

DOI: 10.11830/ISSN.1000-5013.2012.03.0265, PP. 265-268

Keywords: 带隙基准源,电源噪声抑制比,低工作电压,低功耗,模拟IP

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Abstract:

采用CSMC0.35μm工艺,通过在电源和带隙基准源电路间插入电流源缓冲级的方法,设计提高带隙基准源电源噪声抑制能力的带隙基准源.在最低工作电压不变的情况下,所设计的带隙基准电源大幅度提高了电路的电源抑制比,且功耗低.仿真结果表明:电源抑制比值为110dB/40dB,Iq=12μA,Vmin=2.4V,可作为模拟IP(知识产权)且易集成于单片系统中.

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