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降低B3G系统中MIMO接收机复杂度的方法

Keywords: 接收机,正交频分复用,现场可编程门阵列

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Abstract:

为降低MIMO(多入多出)接收机的FPGA(现场可编程门阵列)实现对资源的消耗,对V-BLAST(垂直-贝尔实验室分层空时码)译码算法进行了简化。使用位宽缩减技术减少算法实现所占用的资源。同时利用符号保护截止技术保障定点运算的性能.仿真显示其性能接近于Golden译码算法,同时复杂度相比Golden译码算法大大降低.对实现方法在Xilinx公司的VirtexIIPro系列FPGA中的资源使用情况进行了统计,并在B3GTDD(时分双工)实验验证平台上进行了验证.结果表明:该实现方法可用于B3GTDD系统的MIMO接收机的硬件实现.

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