An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H

This paper presents a 6？bit, 11？MS/s time-interleaved pipeline A/D converter design. The specification process, from block level to elementary circuits, is gradually covered to draw a design methodology. Both power consumption and mismatch between the parallel chain elements are intended to be reduced by using some techniques such as double and bottom-plate sampling, fully differential circuits, RSD digital correction, and geometric programming (GP) optimization of the elementary analog circuits (OTAs and comparators) design. Prelayout simulations of the complete ADC are presented to characterize the designed converter, which consumes 12？mW while sampling a 500？kHz input signal. Moreover, the block inside the ADC with the most stringent requirements in power, speed, and precision was sent to fabrication in a CMOS 0.35？μm AMS technology, and some postlayout results are shown. 1. Introduction The ADC design for a multistandard receiver system has different ways to be developed seeing that both the involved standards and the selected architecture face their own drawbacks and implementation issues. A multistandard receiver is not only a combination of isolated systems operating under each of the standards, but a system capable of working in an efficient way under those dynamic conditions. To do that, some desired capabilities are reconfigurable computing and the possibility of sharing and reusing as many blocks as possible between the operation modes. The time-interleaved pipeline architecture is frequently used to satisfy the previous requirements in high speed, moderate resolution applications [1–3]. Its main advantage is the flexibility, hence different number of time-interleaved branches and pipeline stages can be enabled/disabled to configure variable resolution and sampling frequency, thus leading to a reconfigurable system. Figure 1 shows a 2-channel, 4-stage version of the architecture, which could provide 12 bits @ 2.75？MS/s and 6 bits @ 11？MS/s for a GSM/Bluetooth receiver. There are, however, some drawbacks related to the parallelism of time-interleaved pipeline ADCs, such as channel offset, gain and timing mismatch. A front-end sample and hold (S&H) circuit is the most straightforward way to avoid timing skew between channels, as shown in Figure 1 [3]. After this S&H block operating at the full-sample rate of the converter, input signals are not anymore continuous. Thus, exact sampling moments of the first pipeline stages over these new ideally constant input signals are no longer critical. Additionally, if double sampling techniques are used,