Chattopadhyay S, Roychoudhury A. Unified cache modeling for wcet analysis and layout optimizations[C]//Real-Time Systems Symposium, 30th IEEE. Washington, USA: IEEE, 2009:47-56.
[2]
Hardy D, Puaut I. WCET analysis of multi-level non-inclusive set-associative instruction caches[C]//Real-Time Systems Symposium. Barcelona, Spain: IEEE, 2008:456-466.
[3]
VanderWiel S P, Lilja D J. When caches aren\'t enough: data prefetching techniques[J]. Computer, 1997,30(7):23-30.
[4]
Theiling H, Ferdinand C, Wilhelm R. Fast and precise WCET prediction by separated cache and path analyses[J]. Real-Time Systems, 2000,18(2-3):157-179.
[5]
Tang J, Liu S, Gu Z, et al. Prefetching in embedded mobile systems can be energy-efficient[J]. Computer Architecture Letters, 2011,10(1):8-11.
[6]
Lee M, M in S, Kim C. A worst case timing analysis technique for instruction prefetch buffers[J]. Microprocessing and Microprogramming, 1994,40(10):681-684.
[7]
Chen K, Malik S, August D I. Retargetable static timing analysis for embedded software[C]//Proceedings of the 14th international symposium on Systems Synthesis. Montréal,Canada: ACM, 2001:39-44.
[8]
Yan J, Zhang W. WCET analysis of instruction caches with prefetching[J]. ACM SIGPLAN Notices, 2007,42(7):175-184.
[9]
Ni F, Long X, Wan H, et al. Using basic block based instruction prefetching to optimize WCET analysis for real-time applications[C]//Proceedings of the 2012 13th International Conference on Parallel and Distributed Computing, Applications and Technologies. Beijing: IEEE Computer Society, 2012:459-466.
[10]
Aparicio L C, Segarra J, Rodríguez C, et al. Combining prefetch with instruction cache locking in multitasking real-time systems[C]//Proceedings of Embedded and Real-Time Computing Systems and Applications (RTCSA), 2010 IEEE 16th International Conference on Macau SAR. China: IEEE, 2010:319-328.
[11]
Paolieri M, Qui？ones E, Cazorla F J, et al. Hardware support for WCET analysis of hard real-time multicore systems[C]//Proceedings of ACM SIGARCH Computer Architecture News. Washington, USA: ACM, 2009,37(3):57-68.
[12]
Li X, Liang Y, Mitra T, et al. Roychoudhury. Chronos: a timing analyzer for embedded software[J]. Science of Computer Programming, 2007,69(1):56-67.
[13]
Callahan D, Kennedy K, Porterfield A. Software prefetching[J]. ACM SIGOPS Operating Systems Review, 1991,25(Special Issue):40-52.
[14]
Zhang C, Vahid F, Lysecky R. A self-tuning cache architecture for embedded systems[J]. ACM Transactions on Embedded Computing Systems (TECS), 2004,3(2):407-425.
[15]
Thoziyoor S, Muralimanohar N, Ahn J H, et al. CACTI 5.1[S]. Palo Alto: HP Laboratories, 2008.
