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一种小面积的基-3蝶形单元设计

Keywords: 单精度浮点,基-3,FFT,兼容缩放,硬件资源

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Abstract:

为减少该蝶形单元在硬件实现中的资源消耗,提出了一种基于单精度浮点运算的基-3蝶形单元设计.采用兼容缩放的方法来解决该蝶形单元中乘法运算,其中√3采用的缩放因子为223.与√3的乘法操作采用有限个定点加法器来实现.通过理论分析,该方法减少了加法器的个数,同时减少了寄存器的数量.通过对比得出,本文采用的方法在原有的基础上减少了1个加法器和2个48位寄存器.此外,基-3蝶形单元采用降低乘法操作数目的实现形式,使得与实数相乘的乘法数目由原来的4个降为2个.实验结果表明,本文采用的方法节省了基-3蝶形单元实现所需的硬件资源,为降低基-3FFT实现的资源消耗打下了基础.

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