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基于FPGA的配电网暂态实时仿真研究(二):系统架构与算例验证

DOI: 10.13334/j.0258-8013.pcsee.2014.04.015, PP. 628-634

Keywords: 配电网,暂态实时仿真,现场可编程门阵列,系统架构

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Abstract:

有源配电网暂态实时仿真需要较强的计算能力作为支持,因此提出基于现场可编程门阵列的有源配电网暂态实时仿真中系统级并行、模块级并行以及底层并行的多层级并行架构,并研究了各层级并行的实现方式。利用模块级并行以及底层并行的设计思想,使用VerilogHDL语言开发了基于浮点数运算的配电网暂态实时仿真系统。为验证该实时仿真系统的有效性,选取典型配电网络并以2??s的仿真步长进行了实时仿真测试,充分验证了所提配电网暂态实时仿真系统在仿真速度、仿真规模方面的优势,通过与Matlab/SimPowerSystems的计算结果进行比较,验证了该系统的仿真精度。

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