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Subrina S, Kotchetkov D, Balandin A A. Heat removal in silicon-on-insulator integrated circuits with graphene lateral heat spreaders.IEEE Electron Device Lett, 2009, 30: 1281-1283
[10]
Wang Z, Dong G, Yang Y T, et al. Crosstalk noise voltage of coupling RC interconnect with temperature distribution. Chinese J Electron,2010, 19: 43-47
[11]
Wang Z, Dong G, Yang Y T, et al. Study on clock skew of unsymmetrical RLC interconnect tree with temperature distribution (in Chinese).Acta Phys Sin, 2010, 59: 5646-5651
[12]
Sundaresan K, Mahapatra N R. An analysis of timing violations due to spatially distributed thermal effects in global wires. In: Levitan P S,Fix L, eds. Proceedings of ACM/IEEE DAC, 2007 June 4-8, San Diego. New York: Association for Computing Machinery Press, 2007.515-520
[13]
Im S, Banerjee K. Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs. In: Marek J, Illing M,eds. IEEE Int Electron Devices Meeting, 2000 Dec 10-13, San Francisco. Hong Kong: the University of Hong Kong Press, 2001. 727-730
[14]
Ni M.[J].Memik S O. Self-heating-aware optimal wire sizing under Elmore delay model. In: Lauwereins R, Madsen J, eds. Design, Automation& Test in Europe Conference & Exhibition.2007,:-
[15]
? Datta B, Burleson W P. Low power on-chip thermal sensors based on wires. In: Mooney V, Zhao L, Hasler P, eds. IFIP Int Conf on VeryLarge Scale Integration, 2007 Oct 15-17, Atlanta. New York: Springer-Verlag, 2008. 258-263
[16]
Che F X, Zhang X, Zhu W H, et al. Reliability evaluation for copper/low-k structures based on experimental and numerical methods. IEEETrans Device Mater Relia, 2008, 8: 455-463
[17]
ESIA, JEITA, KSIA, et al. International technology roadmap for semiconductors. Technical Report, ITRS for Semiconductors 2007 edition:Interconnect, the ITRS Organization. 2007