1 Turner S E, Chan R T, Feng J T. ROM-based direct digital synthesizer at 24 GHz clock frequency in InP DHBT technology. IEEEMicrowave Wireless Compon Lett, 2008, 18: 566-568??
[2]
2 Baek K H, Merlo E, Choe M J, et al. A 1.7 GHz 3V direct digital frequency synthesizer with an on-chip DAC in 0.35 μm SiGe BiCMOS.In: IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2005, San Francisco, CA. 114-587
[3]
3 Chen G P, Wu D Y, Jin Z, et al. A 10 GHz 8-bit direct digital synthesizer implemented in GaAs HBT technology. In: IEEE RadioFrequency Integrated Circuits Symposium (RFIC); 2010, 23-25 May 2010; Anaheim, CA. 425-428
[4]
7 Wu D Y, Chen G P, Chen J W, et al. A 6 GHz direct digital synthesizer MMIC with nonlinear DAC and wave correction ROM. In: IEEERadio Frequency Integrated Circuits Symposium (RFIC), 2010, 23-25 May 2010, Anaheim, CA. 421-424
[5]
8 Kwok C Y, Sheng N H, Asbeck P M. 300 ps 4 K read-only memory implemented with AlGaAs/GaAs HBT technology. Electron Lett,1994, 30: 759-760??
[6]
4 Yang B D, Choi J H, Han S H, et al. An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/A converter. IEEE JSolid-State Circuits, 2004, 39: 761-774??
[7]
5 Strollo A G M, De Caro D, Petra N. A 630 MHz, 76 mW direct digital frequency synthesizer using enhanced ROM compression technique.IEEE J Solid-State Circuits, 2007, 42: 350-360
[8]
6 Huang C C, Jhuang G L, Wang C C. A high-SFDR direct digital frequency synthesizer with embedded error-compensation CMOS OTPROM for wireless receivers. Microwave Opt Technol Lett, 2009, 51: 1695-1699??
[9]
9 Takahashi O, Aoki N, Silberman J, et al. A 1-GHz logic circuit family with sense amplifiers. IEEE J Solid-State Circuits, 1999, 34:616-622??
[10]
10 Metzger A G, Asbeck P M. A 64-bit high-speed read-write look-up table memory implemented in GaAs HBT. In: Bipolar/BiCMOSCircuits and Technology Meeting, 2006; Maastricht. 2006, 1-4
[11]
11 Manandhar S, Turner S E, Kotecki D E. 36-GHz, 16×6-bit ROM in InP DHBT technology suitable for DDS application. IEEE JSolid-State Circuits, 2007, 42: 451-456
[12]
12 Yamaguchi K, Nambu H, Kanetani K, et al. A 1.5-ns access time, 78 μm2 memory-cell size, 64-kb ECL-CMOS SRAM. IEEE J Solid-StateCircuits, 1992, 27: 167-174