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全数字硬件化正交锁相环建模与分析

, PP. 148-155

Keywords: 正交锁相环,全数字硬件化,字长模型,有限字长效应

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Abstract:

针对FPGA/ASIC的全定制特性带来的字长优化问题,提出一种基于FPGA/ASIC的全数字硬件化正交锁相环字长建模方法。首先,利用稳定性判据和卷积分别建立系数和内部变量的整数字长模型;然后,依据系统灵敏度及L2范数理论分别对系数和内部变量的小数字长建模,从而只需设定系数准确度指标ε和变量准确度指标ζ,即可设计出满足要求的全数字硬件化正交锁相环,保证在消耗最少资源的前提下,有效避免溢出错误和抑制有限字长效应;最后通过实验,验证了所提模型的可靠性。

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