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基于混沌序列的时序数字电路BIST技术

, PP. 144-149

Keywords: 时序电路,混沌0-1序列,内建自测试,循环冗余校验

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Abstract:

提出一种基于混沌序列的时序数字电路的内建自测试(BIST)技术。采用混沌logistic映射模型迭代运算产生具有白噪声特性的“0-1”随机测试序列,将其作为数字电路内建测试的自动测试图形,并利用循环冗余校验(CRC)特征分析电路分析输出响应,从而得到混沌序列测试图形的响应特征码,通过特征码的不同来检测故障。实验研究表明,由于混沌迭代序列测试图形的施加顺序不唯一,因此对于时序数字电路的故障检测而言,能够比普通M序列测试的故障检测率更高,易于BIST技术实现,并适合于FPGA等大规模可编程逻辑电路的自动测试。

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