Hartenstein R. A decade of reconfigurable computing: a visionary retrospective// 2001 Design, Automation and Test in Europe Conference and Exposition (DATE 2001). Munich: IEEE Press Piscataway, 2001: 642-649.
[2]
Singh H. MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications[J]. IEEE Trans Computers, 2000, 49(5): 465-481.
[3]
Berekovic M. Mapping of video compression algorithms on the ADRES coarse-grain reconfigurable array//MSP7 Workshop on Multimedia and Stream Processors. Barcelona: , 2005: 47-52.
[4]
XPP-III processor overview white paper. 2007-09-03.
[5]
Li Y, Callahan T, Darnell E, et al. Hardware-software co-design of embedded reconfigurable architectures//Proceedings, 37th Design Automation Conference (DAC 2000). Los Angeles: , 2000: 507-512.
[6]
Lee J, Choi K, Dutt N. Compilation approach for coarse-grained reconfigurable architectures[J]. IEEE D&T, 2003: 26-33.
[7]
胡嘉凯, 梁立伟, 蒋建国, 等. 基于TMS320C64xDSP的H.264 整数变换快速实现[J]. 电视技术, 2005(4): 17-19. Hu Jiakai, Liang Liwei, Jiang Jianguo, et al. A fast method to realize integer transform of H.264 based on TMS320C64x DSP[J]. Video Engineering, 2005(4): 17-19.
[8]
Goldstein S C. PipeRench: a reconfigurable architecture and compiler. Computer, 2000, 33(4): 70-77.
[9]
Texas Instruments Inc. TMS320C6000 Assembly Benchmarks at Texas Instruments: C64X DSP Benchmarks. 2003-05-03.