高速层进式NandFlash纠错控制编码

DOI: 10.13190/jbupt.201003.71.hank, PP. 71-74

Keywords: Nand存储器,差错控制编码,Bose-Chaudhuri-Hocquengham

Full-Text   Cite this paper   Add to My Lib

Abstract:

References

[1]	Chang H C, Lin C C, Hsiao T Y, et al. Multi-level memory systems using error control codes//ISCAS04. Ottawa: , 2004: 393-396.
[2]	Zhang Xinmiao, Parhi K K. High-speed architectures for parallel long BCH encoders[J]. IEEE Trans on Very Large Scale Integration (VLSI) Systems, 2005, 13(7): 872-877.
[3]	Wu Yuejian. Low power decoding of BCH codes//ISCAS04. Ottawa:, 2004: 369-372.
[4]	Parhi K K. Eliminating the fanout bottleneck in parallel long BCH encoders[J]. IEEE Trans on Circuits Systems-Part Ⅰ: Regular Papers, 2004, 51(3): 512-516.
[5]	Zhang Jun, Wang Zhigong, Hu Qingsheng, et al. Optimized design for high-speed parallel BCH encoder//IEEE International Workshop on VLSI Design and Video Technology. Nanjing: , 2005: 97-100.
[6]	Chen Yanni, Parhi K K. Small area parallel Chien search architectures for long BCH codes[J]. IEEE Trans on Very Large Scale Integration (VLSI) Systems, 2004, 12(5): 545-549.
[7]	杨健, 王文东. 使用主动前向纠错技术的可扩展的可靠组播协议[J]. 北京邮电大学学报, 2003, 26(1): 50-54. Yang Jian, Wang Wendong. Scalable reliable multicast protocal using active FEC[J]. Journal of Beijing University of Posts and Telecommunications, 2003, 26(1): 50-54.

Full-Text