Henkel J, Wolf W, Chakradhar S. On-chip networks: a scalable, communication centric embedded system design paradigm[C] // Proceedings of the IEEE International Conference on VLSI Design (VLSI Design 2008). Mumbai: IEEE Press, 2004: 845-851.
[2]
Hu Jingcao, Ogras U Y, Marculescu R. System- level buffer allocation for application specific networks-on-chip router design[J]. IEEE Transaction on Computer-aided Design of Integrated Circuits and Systems, 2006, 25(12): 2919-2933.
Wang Liwei, Cao Yang, Li Xiaohui, et al. A buffer allocation algorithm for wormhole routing networks-on-chip[J]. Journal of Beijing University of Posts and Telecommunications, 2008, 31(4): 29-32.
[5]
Barati H, Movaghar A, Barati A, et al. Routing algorithms study and comparing in interconnection networks[C] // Proceedings of 3rd International Conference on Information and Communication Technologies (ICICT 2008). Damascus: IEEE Press, 2008:1-5.
[6]
Bahn J H, Bagherzadeh N. Design of simulation and analytical models for a 2d-meshed asymmetric adaptive router[J]. IET Computer Digital Technology, 2008, 2(1): 63-73.
[7]
Patooghy A, Sarbazi-azad H. Analytical performance modeling of partially adaptive routing in wormhole hypercube[C] // Proceedings of 20th International Parallel and Distributed Processing Symposium (IPDPS 2006). Rhodes Island: IEEE Press, 2006:1-7.
[8]
Duato J, Yalamanchili S, Lionel M. Interconnection networks-an engineering approach[M]. San Francisco: Morgan Kaufmann Publisher, 2003.
[9]
Hu Jingcao, Marculescu R. DyAD-smart routing for networks-on-chip[C] // Proceedings of the 41st Design Automatic Conference (DAC 2004). San Diego: ACM Press, 2004: 260-263.
