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多区间功放预失真方案与FPGA实现

DOI: 10.13190/jbupt.201201.90.chenj, PP. 90-94

Keywords: 数字预失真,可编程逻辑器件,记忆多项式模型,功放,分区间记忆多项式模型

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Abstract:

为了降低通信系统中功放非线性特性带来频谱泄漏对邻带信号的干扰,针对使用较为广泛的Doherty功放,提出了分区间记忆多项式功放模型.经过实际测试,新的模型对于Doherty(80W)功放的邻带交调(ACLR)性能比记忆多项式模型有16dB的提升,与其他数字预失真方案相比,其ACLR性能也至少有10dB的改善,且更易用可编程逻辑器件(FPGA)实现.

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