Static
phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs)
dramatically degrades the deterministic jitter performance. To overcome the
issue, this paper presents a new SPO reduction technique for MDLLs. The
technique is based on the observation that the SPO of MDLL is mainly caused by
the non-idealities on charge pump (e.g. sink and source current mismatch), and
control line (e.g. gate leakage of loop filter and voltage controlled delay
line (VCDL) control circuit). With a high gain stage inserting between phase
detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO
has been decreased by a factor equal to the gain of the gain stage. The
effectiveness of the proposed technique is validated by a Simulink model of
MDLL. The equivalent SPO is measured by the power level of reference spur.
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