全部 标题 作者
关键词 摘要

OALib Journal期刊
ISSN: 2333-9721
费用:99美元

查看量下载量

相关文章

更多...
VLSI Design  2014 

On the Use of an Algebraic Signature Analyzer for Mixed-Signal Systems Testing

DOI: 10.1155/2014/465907

Full-Text   Cite this paper   Add to My Lib

Abstract:

We propose an approach to design of an algebraic signature analyzer that can be used for mixed-signal systems testing. The analyzer does not contain carry propagating circuitry, which improves its performance as well as fault tolerance. The common design technique of a signature analyzer for mixed-signal systems is based on the rules of an arithmetic finite field. The application of this technique to the systems with an arbitrary radix is a challenging task and the devices designed possess high hardware complexity. The proposed technique is simple and applicable to systems of any size and radix. The hardware complexity is low. The technique can also be used in arithmetic/algebraic coding and cryptography. 1. Introduction Signature analysis has been widely used for digital and mixed-signal systems testing [1–12]. Mixed-signal systems consist of both digital and analog circuits; however the signature analysis method is only applicable to the subset of these systems that have digital outputs (such as analog-to-digital converters, measurement instruments, etc.). Signature analysis can be employed as an external test solution or can be embedded into the system under test. In the built-in implementation, a circuit under test (CUT) of digital or mixed-signal nature is fed by test stimuli, while the output responses are compacted by a signature analyzer (SA), as illustrated in Figure 1. The actual signature is compared against the fault-free circuit’s signature and a pass/fail decision is made. A signature of a fault-free circuit is referred to as a reference signature. If the CUT is of a digital nature, the SA essentially constitutes a circuit that computes an algebraic remainder. The reference signature has only one, punctual value, and the decision making circuit consists of a simple digital comparator. If the CUT is of a mixed-signal nature, the SA computes an arithmetic residue. In this case, the reference signature becomes an interval value and the decision making circuit uses a window comparator. Figure 1: Built-in signature analysis of a circuit under test. Design methods for an algebraic signature analyzer have been well developed in error-control coding [13]. A remainder calculating circuit for an arbitrary base (binary or nonbinary) can be readily designed for a digital CUT of any size. In contrast, it is much harder to design a residue calculating circuit, specifically for a nonbinary base [14]. Furthermore, due to the presence of carry propagating circuitry, the implementation complexity and error vulnerability of the residue calculating circuit

References

[1]  R. Frohwerk, “Signature analysis: a new digital field service method,” Hewlett-Packard Journal, vol. 28, no. 9, pp. 2–8, 1977.
[2]  G. J. Starr, J. Qin, B. F. Dutton, C. E. Stroud, F. F. Dai, and V. P. Nelson, “Automated generation of built-in self-test and measurement circuitry for mixed-signal circuits and systems,” in Proceedings of the 15th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT '09), pp. 11–19, October 2009.
[3]  D. K. Pradhan and S. K. Gupta, “A new framework for designing and analyzing BIST techniques and zero aliasing compression,” IEEE Transactions on Computers, vol. 40, no. 6, pp. 743–763, 1991.
[4]  C. Stroud, J. Morton, T. Islam, and H. Alassaly, “A mixed-signal builtin self-test approach for analog circuits,” in Proceedings of the Southwest Symposium on Mixed-Signal Design, pp. 196–201, 2003.
[5]  N. Nagi, A. Chatterjee, H. Yoon, and J. A. Abraham, “Signature analysis for analog and mixed-signal circuit test response compaction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 6, pp. 540–546, 1998.
[6]  N. Nagi, A. Chatterjee, and J. A. Abraham, “Signature analyzer for analog and mixed-signal circuits,” in Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 284–287, October 1994.
[7]  S. Mir, M. Lubaszewski, V. Liberali, and B. Courtois, “Built-in self-test approaches for analogue and mixed-signal integrated circuits,” in Proceedings of the IEEE 38th Midwest Symposium on Circuits and Systems, vol. 2, pp. 1145–1150, Rio de Janeiro, Brazil, August 1995.
[8]  J. Rajski and J. Tyszer, “The analysis of digital integrators for test response compaction,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 39, no. 5, pp. 293–301, 1992.
[9]  L. Wei and L. Jia, “An apprach to analong and mixed-signal BIST based-on pseudorandom testing,” in Proceedings of the IEEE International Conference on Communications, Circuits and Systems, (ICCCAS '08), pp. 1192–1195, Fujian, China, May 2008.
[10]  F. Corsi, C. Marzocca, and G. Matarrese, “Defining a BIST-oriented signature for mixed-signal devices,” in Proceedings of the IEEE Southwest Symposium on Mixed-Signal Design, pp. 202–207, 2003.
[11]  S. Demidenko, V. Piuri, V. Yarmolik, and A. Shmidman, “Bist module for mixed-signal circuits,” in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 349–352, 1998.
[12]  T. Damarla, “Implementation of signature analysis for analog and mixed signal circuits,” U.S. Patent 6 367 043, 2002.
[13]  W. W. Peterson and J. Weldon, Error Correcting Codes, MIT Press, Cambridge, Mass, USA, 2nd edition, 1972.
[14]  V. Geurkov, “Optimal choice of arithmetic compactors for mixed-signal systems,” in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT '12), pp. 182–186, October 2012.
[15]  S. Lin and D. Costello, Error Control Coding, Pearson Education, Upper Saddle River, NJ, USA, 2004.
[16]  V. Geurkov, V. Kirischian, L. Kirischian, and R. Sedaghat, “Concurrent testing of analog-to-digital converters,” i-manager's Journal on Electronics Engineering, vol. 1, no. 1, pp. 8–14, 2010.
[17]  MC9S12DT128 Device User Guide, V02.11, Motorola, May 2004, http://www.freescale.com/.

Full-Text

Contact Us

service@oalib.com

QQ:3279437679

WhatsApp +8615387084133