Optimization of Fractional-N-PLL Frequency Synthesizer for Power Effective Design

We are going to design and simulate low power fractional-N phase-locked loop (FNPLL) frequency synthesizer for industrial application, which is based on VLSI. The design of FNPLL has been optimized using different VLSI techniques to acquire significant performance in terms of speed with relatively less power consumption. One of the major contributions in optimization is contributed by the loop filter as it limits the switching time between cycles. Sigma-delta modulator attenuates the noise generated by the loop filter. This paper presents the implementation details and simulation results of all the blocks of optimized design. 1. Introduction For many manufacturers and product developers, it is a good idea to reduce power consumption in electronic products. It is also an important idea to gain competitive advantage in an increasingly power hungry world. Low power consumption gives many benefits to designers and to users; for example, the main advantage is that it reduces stringent cooling requirements and it results in inexpensive and more compact products [1]. The rapid rise in power requirements has promoted governments and industry to increase energy efficiency and design low power components. The majority of frequency synthesis techniques fall into two categories: either direct frequency synthesis or indirect frequency synthesis [2]. To achieve fine frequency steps, the direct frequency synthesis technique is used because it is based on using digital techniques. To generate multiples (integer or noninteger) of a reference frequency, indirect frequency synthesis is used because it is based on a phase-locked loop (PLL). Here, the latter technique is used because we are going to implement PLL. It is used to generate a signal whose phase is related to the phase of the input signal and this signal is called an output signal of the PLL. The input signal is called the “reference” signal. In a feedback loop, the oscillator is controlled by the output signal from the phase detector [3, 4]. The circuit compares the phase of a signal obtained from its output oscillator with the phase of the input signal to keep the phases matched by adjusting the frequency of its oscillator. A phase locked loop (PLL) architecture has two types, a Fractional-N PLL (FNPLL) and an integer-N PLL [5]. For a given frequency resolution, the latter has high reference frequency than the former, and, hence, the loop bandwidth which is limited to 10% of the reference frequency can be set larger in the FNPLL than in the integer-N-PLL. Therefore, the latter architecture is used for faster