Image interpolation is a method of estimating the values at unknown points using the known data points. This procedure is used in expanding and contrasting digital images. In this survey, different types of interpolation algorithm and their hardware architecture have been analyzed and compared. They are bilinear, winscale, bi-cubic, linear convolution, extended linear, piecewise linear, adaptive bilinear, first order polynomial, and edge enhanced interpolation architectures. The algorithms are implemented for different types of field programmable gate array (FPGA) and/or by different types of complementary metal oxide semiconductor (CMOS) technologies like TSMC 0.18 and TSMC 0.13. These interpolation algorithms are compared based on different types of optimization such as gate count, frequency, power, and memory buffer. The goal of this work is to analyze the different very large scale integration (VLSI) parameters like area, speed, and power of various implementations for image interpolation. From the survey followed by analysis, it is observed that the performance of hardware architecture of image interpolation can be improved by minimising number of line buffer memory and removing superfluous arithmetic elements on generating weighting coefficient. 1. Introduction In digital image scaling, image interpolation algorithms are used to convert an image from one resolution to another resolution without losing the visual content in the image. In the colour, image interpolation is the process of estimating the missing colour samples to reconstruct a full colour image [1]. Image scaling is widely used in many fields, ranging from consumer electronics, such as digital camera, mobile phone, tablet, display devices and medical imaging like computer assisted surgery (CAS) and digital radiographs [2]. In many applications, from consumer electronics to medical imaging, it is desirable to improve the restructured image quality and processing performance of hardware implementation [3]. For example, a video source with a 640 × 480 video graphics arrays (VGA) resolution may need to fit the 1920 × 1080 resolution of a high definition multimedia interface (HDMI). Image up scaling [4] methods are implemented for a variety of computer equipments like printers, digital television, media players, image processing systems, graphics renderers, and so on. On the other hand, high resolution image may need to be scaled down to a small size in order to fit the lower resolution of small liquid crystal display panels. That is, the image scaling is a challenging and very significant
References
[1]
I. Pekkucuksen and Y. Altunbasak, “Multiscale gradients-based colour filter array interpolation,” IEEE Transactions on Image Processing, vol. 22, no. 1, pp. 157–165, 2013.
[2]
T. M. Lehmann, C. G?nner, and K. Spitzer, “Survey: interpolation methods in medical image processing,” IEEE Transactions on Medical Imaging, vol. 18, no. 11, pp. 1049–1075, 1999.
[3]
S.-L. Chen, H.-Y. Huang, and C.-H. Luo, “A low-cost high-quality adaptive scalar for real-time multimedia applications,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 21, no. 11, pp. 1600–1611, 2011.
[4]
A. Giachetti and N. Asuni, “Real-time artifact-free image upscaling,” IEEE Transactions on Image Processing, vol. 20, no. 10, pp. 2760–2768, 2011.
[5]
I. Andreadis and A. Amanatiadis, “Digital image scaling,” in Proceedings of the IEEE Instrumentation and Measurement Technology Conference (IMTC '05), pp. 2028–2032, Ottawa, Canada, May 2005.
[6]
S. P. Jaiswal, V. Jakhetiya, A. Kumar, and A. K. Tiwari, “A low complex context adaptive image interpolation algorithm for real time applications,” in Proceedings of the IEEE International Conference on Instrumentation and Measurement Technology (MTC '12), pp. 969–972, 2012.
[7]
C.-C. Huang, P.-Y. Chen, and C.-H. Ma, “A novel interpolation chip for real-time multimedia applications,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 22, no. 10, pp. 1512–1525, 2012.
[8]
L. Deng, K. Sobti, Y. Zhang, and C. Chakrabarti, “Accurate area, time and power models for FPGA-based implementations,” Journal of Signal Processing Systems, vol. 63, no. 1, pp. 39–50, 2011.
[9]
C.-H. Kim, S.-M. Seong, J.-A. Lee, and L.-S. Kim, “Winscale: an image-scaling algorithm using an area pixel model,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 13, no. 6, pp. 549–553, 2003.
[10]
C.-C. Lin, Z.-C. Wu, W.-K. Tsai, M.-H. Sheu, and H.-K. Chiang, “The VLSI design of winscale for digital image scaling,” in Proceedings of the 3rd International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIHMSP '07), vol. 2, pp. 511–514, November 2007.
[11]
C.-C. Lin, M.-H. Sheu, H.-K. Chiang, C. Liaw, and Z.-C. Wu, “The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '08), pp. 480–483, May 2008.
[12]
C.-C. Lin, M.-H. Sheu, H.-K. Chiang, W.-K. Tsai, and Z.-C. Wu, “Real-time FPGA architecture of extended linear convolution for digital image scaling,” in Proceedings of the International Conference on Field-Programmable Technology (FPT '08), pp. 381–384, Taipei, Taiwan, December 2008.
[13]
C.-C. Lin, M.-H. Sheu, H.-K. Chiang, Z.-C. Wu, J.-Y. Tu, and C.-H. Chen, “A low-cost VLSI design of extended linear interpolation for real time digital image processing,” in Proceedings of the International Conference on Embedded Software and Systems (ICESS '08), pp. 196–202, July 2008.
[14]
C.-C. Lin, M.-H. Sheu, H.-K. Chiang, C. Liaw, Z.-C. Wu, and W.-K. Tsai, “An efficient architecture of extended linear interpolation for image processing,” Journal of Information Science and Engineering, vol. 26, no. 2, pp. 631–648, 2010.
[15]
P.-Y. Chen, C.-Y. Lien, and C.-P. Lu, “VLSI implementation of an edge-oriented image scaling processor,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 9, pp. 1275–1284, 2009.
[16]
M. A. Nu?o-Maganda and M. O. Arias-Estrada, “Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig '05), pp. 1–8, September 2005.
[17]
S.-L. Chen, “VLSI implementation of a low cost high quality image scaling processer,” IEEE Transactions on Circuit and System: Express Briefs, vol. 60, no. 1, pp. 31–35, 2013.
[18]
S.-L. Chen, “VLSI implementation of an adaptive edge-enhanced image scalar for real-time multimedia applications,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 23, no. 9, pp. 1510–1522, 2013.
[19]
C.-C. Lin, M.-H. Sheu, C. Liaw, and H.-K. Chiang, “Fast first-order polynomials convolution interpolation for real-time digital image reconstruction,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 20, no. 9, pp. 1260–1264, 2010.
[20]
C.-C. Lin, C. Liaw, and C.-T. Tsai, “A piecewise linear convolution interpolation with third-order approximation for real-time image processing,” in Proceedings of the IEEE International Conference on Systems, Man and Cybernetics (SMC '10), pp. 3632–3637, October 2010.
[21]
S. A. Fahmy, “Generalised parallel bilinear interpolation architecture for vision systems,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig '08), pp. 331–336, December 2008.
[22]
K. T. Gribbon and D. G. Bailey, “A novel approach to real-time bilinear interpolation,” in Proceedings of the 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA '04), pp. 126–131, January 2004.