A novel low power CMOS imaging system with smart image capture and adaptive complexity 2D-Discrete Cosine Transform (DCT) is proposed. Compared with the existing imaging systems, it involves the smart image capture and image processing stages cooperating together and is very efficient. The type of each 8 × 8 block is determined during the image capture stage, and then input into the DCT block, along with the pixel values. The 2D-DCT calculation has adaptive computation complexity according to block types. Since the block type prediction has been moved to the front end, no extra time or calculation is needed during image processing or image capturing for prediction. The image sensor with block type decision circuit is implemented in TSMC 0.18 μm CMOS technology. The adaptive complexity 2D-DCT compression is implemented based on Cyclone EP1C20F400C8 device. The performance including the image quality of the reconstructed picture and the power consumption of the imaging system are compared to those of traditional CMOS imaging systems to show the benefit of the proposed low power algorithm. According to simulation, up to 46% of power consumption can be saved during 2D DCT calculation without extra loss of image quality for the reconstructed pictures compared with the conventional compression methods.
References
[1]
Yadid-Pecht, O.; Etienne-Cummings, R. CMOS Imagers: From Phototransduction to Image Processing; Kluwer: Norwell, MA, USA, 2004.
[2]
Fish, A.; Yadid-Pecht, O. Low-Power “Smart” CMOS Image Sensors. In Proceedings of the IEEE International Symposium on Circuits and Systems, Washington DC, USA, 18–21 May 2008; pp. 1408–1411.
[3]
Xu, C.; Zhang, W.; Ki, W. A 1.0 V VDD CMOS active-pixel sensor with complementary pixel architecture and pulsewidth modulation fabricated with a 0.25 μm CMOS process. IEEE J. Solid-State Circuits 2002, 37, 1853–1859, doi:10.1109/JSSC.2002.804346.
[4]
Shen, C.; Xu, C.; Huang, R.; Zhang, W.; Ko, P.K.; Chan, M. A New APS Architecture on SOI Substrate for Low Voltage Operation. In Proceedings of the 9th International Symposium on IC Technology, Systems & Applications, Singapore, 3–5 September 2001; pp. 275–278.
[5]
Fish, A.; Hamami, S.; Yadid-Pecht, O. CMOS image sensors with self-powered generation capability. IEEE Trans. Circuits Syst. II 2006, 53, 131–135.
[6]
Shi, C.; Law, M.K.; Bermak, A. A novel asynchronous pixel for an energy harvesting CMOS image sensor. IEEE Trans. VLSI Syst. 2011, 19, 118–129, doi:10.1109/TVLSI.2009.2028570.
[7]
Gao, Q.; Yadid-Pecht, O. Dual VDD Block Based CMOS Image Sensor–Preliminary Evaluation. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, 15–19 May 2011; pp. 1820–1823.
[8]
Gao, Q.; Yadid-Pecht, O. A low power block based CMOS image sensor with dual VDD. IEEE Sens. J. 2012, 12, 747–755, doi:10.1109/JSEN.2011.2156405.
[9]
Loeffler, C.; Lightenberg, A.; Moschytz, G.S. Practical Fast 1-D DCT Algorithms with 11-Multiplications. In Proceedings of the International Conference on AcousticsSpeechand Signal Processing-89, Glasgow, UK, 23–26 May 1989; Volume 2, pp. 988–991.
[10]
Thoudam, V.P.S.; Bhaumik, B.; Chatterjee, S. Ultra Low Power Implementation of 2-D DCT for Image/Video Compression. In Proceedings of International Conference on Computer Applications & Industrial Electronics (ICCAIE 2010), Kuala Lumpur, Malaysia, 5–7 December 2010; pp. 532–536.
[11]
Sun, C.-C.; Ruan, S.-J.; Heyne, B.; Goetze, J. Low-power and high-quality Cordic-based Loeffler DCT for signal processing. Circuits Devices Syst. IET 2007, 1, 453–461, doi:10.1049/iet-cds:20060289.
[12]
Tran, T.D. The binDCT: Fast multiplierless approximation of the DCT. IEEE Signal Process. Lett. 2000, 7, 141–144, doi:10.1109/97.844633.
[13]
Sung, T.-Y.; Shieh, Y.-S.; Yu, C.-W.; Hsin, H.-C. High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation. In Proceedings of the 7th International Conference on Parallel and Distributed ComputingApplications and Technologies, Taipei, Taiwan, 4–7 December 2006; pp. 191–196.
[14]
Jeong, H.; Kim, J.; Cho, W.-K. Low-power multiplierless DCT architecture using image data correlation. IEEE Trans. Consum. Electron. 2004, 50, 262–267, doi:10.1109/TCE.2004.1277872.
[15]
Xanthopoulos, T.; Chandrakasan, A.P. A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization. IEEE J. Solid-State Circuits 2000, 35, 740–750, doi:10.1109/4.841502.
[16]
Pillai, L. Video Compression Using DCT; Xilinx: San Jose, CA, USA, 2002.
[17]
Loeve, M. Probability Theory, Graduate Texts in Mathematics, 4th ed. ed.; Springer-Verlag: Berlin, Germany, 1977.
