The increasing popularity of DVFS (dynamic voltage frequency scaling) schemes for portable low power applications demands highly efficient on-chip DC-DC converters. The primary aim of this work is to enable increased efficiency of on-chip DC-DC conversion for near-threshold operation of multicore chips. The idea is to supply nominal (high) off-chip voltage to the cores which are then “voltage-stacked” to generate the near-threshold (low) voltages based on Kirchhoff’s voltage law through charge recycling. However, the effectiveness of this implicit down-conversion is affected by the current imbalance among the cores. The paper presents a design methodology and optimization strategy for highly efficient charge recycling on-chip regulation using a push-pull switched capacitor (SC) circuit. A dual-boundary hysteretic feedback control circuit has been designed for stacked loads. A stacked-voltage domain with its self-regulation capability combined with a SC converter has shown average efficiency of 78%–93% for 2:1 down-conversion with I Load (max) of 200 mA and workload imbalance varying from 0–100%.
References
[1]
Dreslinski, R.G.; Wieckowski, M.; Blaauw, D.; Sylvester, D.; Mudge, T. Near-threshold computing: reclaiming moore's law through energy efficient integrated circuits. Proc. IEEE 2010, 98, 253–266, doi:10.1109/JPROC.2009.2034764.
[2]
Yu, P.; Xin, Z.; Huang, J.; Muramatsu, A.; Nomura, M.; Hirairi, K.; Takata, H.; Sakurabayashi, T.; Miyano, S.; Takamiya, M.; et al. Misleading Energy and Performance Claims in Sub/Near Threshold Digital Systems. In Proceedings of 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, 7–11 November 2010; pp. 625–631.
[3]
Patounakis, G.; Li, Y.W.; Shepard, K.L. A fully integrated on-chip DC-DC conversion and power management system. IEEE J. Solid-State Circuits 2004, 39, 443–451.
[4]
Hanh-Phuc, L.; Sanders, S.R.; Alon, E. Design Techniques for fully integrated switched-capacitor DC-DC converters. IEEE J. Solid-State Circuits 2011, 46, 2120–2131.
[5]
Mazumdar, K.; Stan, M. Breaking the Power Delivery Wall Using Voltage Stacking. In Proceedings of the Great Lakes Symposium on VLSI, Salt Lake City, UT, USA, 3–4 May 2012; pp. 51–54.
[6]
Lee, S.K.; Brooks, D.; Wei, G.-Y. Evaluation of Voltage Stacking For Near-Threshold Multicore Computing. In Proceedings of the 2012 ACM/IEEE International Symposium on Low Power Electronics and Design, Redondo Beach, California, USA, 30 July–01 August 2012; pp. 373–378.
[7]
Rajapandian, S.; Zheng, X.; Shepard, K.L. Implicit DC-DC downconversion through charge-recycling. IEEE J. Solid-State Circuits 2005, 40, 846–852.
[8]
Kanev, S. Motivating Software-Driven Current Balancing in Flexible Voltage-Stacked Multicore Processors. Bachelor’s Thesis, Harvard University, Cambridge, MA, USA, May 2012.
[9]
Mazumdar, K.; Stan, M.R. Charge Recycling On-Chip DC-DC Conversion for Near-Threshold Operation. In Proceedings of the Subthreshold Microelectronics Conference (SubVT), Waltham, MA, UK, 9–10 October 2012; pp. 1–3.
[10]
Brodersen, R.W.; Horowitz, M.A.; Markovic, D.; Nikolic, B.; Stojanovic, V. Methods for True Power Minimization. In Proceedings of the 2002 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), New York, NY, USA, 10–14 November 2002; pp. 35–42.
[11]
Zhenyu, Q.; Ziegler, M.; Kosonocky, S.V.; Rabaey, J.M.; Stan, M.R. Multi-dimensional Circuit and Micro-architecture Level Optimization. In Proceedings of the 8th International Symposium on Quality Electronic Design( ISQED), San Jose, CA, USA, 26–28 March 2007; pp. 275–280.
[12]
Mazumdar, K.; Stan, M.R. Breaking the 3-D IC Power Delivery Wall. In Proceedings of the 2012 Asilomar Conference on Signals, Systems and Computers, Asilomar, CA, USA, 4–7 Novmber 2012.
[13]
Seeman, M.D. A Design Methodology for Switched-Capacitor DC-DC Converters. Ph.D. Thesis, University of California, Oakland, CA , USA, 2009.
[14]
Ng, V.W.S. Switched Capacitor DC-DC Converter: Superior Where the Buck Converter has Dominated. Ph.D. Thesis, University of California, Oakland, CA, USA, 2011.
[15]
Van Breussegem, T.M.; Steyaert, M.S.J. Monolithic capacitive DC-DC converter with single boundary-multiphase control and voltage domain stacking in 90 nm CMOS. IEEE J. Solid-State Circuits 2011, 46, 1715–1727.
[16]
Jain, R.; Sanders, S. A 200 mA switched capacitor voltage regulator on 32 nm CMOS and regulation schemes to enable DVFS. In Proceedings of the 14th European Conference, Birmingham, UK, 30 August–1 September 2011; pp. 1–10.
[17]
Fick, D.; Dreslinski, R.G.; Giridhar, B.; Gyouho, K.; Sangwon, S.; Fojtik, M.; Satpathy, S.; Yoonmyung, L.; Daeyeon, K.; Liu, N.; et al. Centip3De: A 3930 DMIPS/W Configurable Near-Threshold 3D Stacked System with 64 ARM Cortex-M3 Cores. In Proceedings of the 2012 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA, 19–23 Feberary 2012; pp. 190–192.
