A review is given of more than a dozen subtopics within the general study of ferroelectrics, with emphasis upon controversies, unsolved problems, and prospects for the next decade, including pure science and industrial applications. The review emphasizes work over the past two years, from 2010 to 2012. 1. Introduction Ferroelectrics have undergone a minor renaissance in the past twenty years with the development of high-quality thin (<300？nm) oxide films, capable of performing switching at the 5？V standard logic level for silicon transistors [1, 2]. The general field of integrated ferroelectrics is not limited to memory devices entailing polarization reversal but includes such things as electrically controlled tunnel junctions, [3, 4] which are much more demanding in their thickness requirements (<7？nm), or electrocaloric cooling devices [5, 6], THz emitters [7, 8], resistive random access memories (RRAMS) [9, 10], photochromics [11], domain nanoelectronics [12, 13], flexible polymeric ferroelectrics [14, 15], and photovoltaics [16, 17]. At present there are perhaps 500 laboratories worldwide with R and D interests in ferroelectric films, and the present review is a rather personal viewpoint of what the most promising lines of investigation will be over the next decade. 2. Mott Field Effect Transistors (MOTTFETs) and Ferroelectric-Gated FETs In a typical computer memory the area of the chip is taken up primarily by the capacitors. Historically the capacitance was provided by a very thin silicon-oxide layer grown by exposing the Si chip to oxygen during processing. However, silicon oxide (mostly quartz) has a rather small dielectric constant (ca. 6.0), and hence the capacitance is small even for very thin films. Even using a high-dielectric material (most of which are ferroelectric oxides), the capacitors in a memory take up most of the chip area; in the jargon of the trade, the capacitors leave a large footprint [1]. A possible solution to this problem is to make the active memory element a programmable gate. For example, a ferroelectric gate (FE-FET) can exhibit a very small footprint [18, 19]. Although such FE-FETs have been actively researched for a decade or more, with noticeable progress in Tokyo, their defect is that the gate must be grounded during the READ operation, so that the gate charge is eventually dissipated. This problem can be circumvented by designing logic cells that are large (six transistors per bit—a so-called “6T” design) but have not been commercialized. A promising new direction in this area is to use the FET gate in materials
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