Leakage Power Analysis of Domino XOR Gate

Two new XOR gates are proposed. First proposed circuits adopt hybrid transistor topology in the pull-down network with all transistors being low threshold voltages. A second proposed circuit adopts hybrid topology with dual threshold voltage transistors. Simulation parameters are measured at 25°C and 110°C. First proposed circuit reduces leakage power consumption up to 50% at 25°C and 58% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 14% as compared to standard N-type domino XOR gate. Similarly, second proposed circuit reduces leakage power consumption up to 73% at 25°C and 90% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 39% as compared to standard N-type domino XOR gate. 1. Introduction CMOS XOR gates are the fundamental units, it is used in many VLSI applications such as adders and microprocessors. CMOS XOR has complex pull up and pull down network, it is being characterized as high power consumption, large layout area, and low speed [1–4]. Domino XOR has small layout area, low power consumption, and improved speed as compared to CMOS XOR [5–7]. Due to its superior performance and low power consumption, domino XOR is being used in many VLSI applications. Standard domino XOR gate requires two phase input signals, one is original and the other is inverted signal. It needs additional inverters to meet the design requirements. The additional inverters not only increase the power consumption but also affect the performance of the circuit. As technology is scaled down, supply voltages are also scaled down to keep the dynamic power at acceptable levels, and at the same time threshold voltage is also scaled down to meet the performance requirements. However, subthreshold leakage and gate oxide leakage currents are increased exponentially with the scaling of threshold voltage and gate oxide thickness , hence power consumption increases and noise immunity decreases. To solve the problem of high subthreshold leakage current, many circuit level techniques have been implemented including body bias control [8], input vector control [9], transistor stack effect [10], dual CMOS [11], and sleep switch [12–14]. Dual domino technique [11] is realized by using low transistor in the evaluation path and high transistor in the precharge path of the circuits. According to Kao, high clock and high inputs (CHIH) are preferable to reduce subthreshold leakage current in dual footless domino gate. Combination of subthreshold and gate oxide leakage current in