DFAL: Diode-Free Adiabatic Logic Circuits

The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. The simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18？μm UMC technology. In proposed inverter the energy efficiency has been improved to almost 60% up to 100？MHz in comparison to conventional CMOS circuits. The present research provides low power high speed results up to 100？MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry. 1. Introduction During the past decade, use of adiabatic logic circuits with energy recovery scheme has received considerable attention in high performance low-power applications such as radio-frequency identification (RFID) tags, smart cards, and sensors because they outperforms in energy efficiency without sacrificing noise immunity and driving ability over their CMOS counterparts. The power consumption in conventional CMOS circuits is proportional to the load capacitance and square of the supply voltage [1, 2], thus researchers have been focused on scaling of the supply voltage and reducing the capacitance to reduce power consumption. For scaling the supply voltage the transistor threshold voltage ( ) must also be scaled down proportionally, however reducing the transistor threshold voltage results in proportional increase in subthreshold leakage current. Further the circuit capacitance can be minimized by reducing the sizes of devices but this affects the driving ability of the circuit [3]. Due to the above limitations, in recent years adiabatic systems have been used to reduce power consumption. Various adiabatic logic circuits have been proposed [3–21] working on the energy recovery [4] principle. The